Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-07-21
2004-11-16
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S037000, C714S043000, C714S048000, C703S020000, C703S021000
Reexamination Certificate
active
06820219
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88119552, filed Nov. 9, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer system testing technology, and more particularly, to an integrated testing method which is capable of performing a test procedure on a number of computer components, which test procedure is performed concurrently in a multitasking manner through software simulation.
2. Description of Related Art
A computer system is typically included with various kinds of components, such as IDE (Integrated Device Electronics) compliant components, USB (Universal Serial Bus) compliant components, PCI/ISA (Peripheral Component Interconnect, Industry Standard Architecture) compliant components, to name just a few. Before shipment, these components have to undergo a test procedure to check the operability thereof. Conventionally, each component is tested by a specifically designed test procedure. In other words, an IDE-compliant component is tested through a test procedure specifically designed to test the IDE-compliant component, while an USB-compliant component is tested through another test procedure specifically designed to test the USB-compliant component.
By a software-simulated test procedure, for example on an IDE-compliant component, a test pattern is generated by a PCI master unit or slave unit, and which is then transferred via a PCI/ISA control unit to the IDE-compliant component to test its responses to the test pattern. This test procedure, however, is inapplicable to testing a USB-compliant component, and the USB-compliant component should be tested by another test procedure specifically designed therefor.
In practice, however, the various components are mounted together on a motherboard and operated in an interrelated manner to share or compete for the resources on the motherboard. Separate test procedures for these components are less likely to discover those problems that will arise from the conflicts between these components. If these conflicts are unresolved in the testing, they might cause the computer system to crash during real operations.
One solution to the foregoing problem is a hardware-based test procedure, in which all the various components, after tape-out, are mounted on a single test board to undergo a test procedure that simulates the real operations of these components. This hardware-based test procedure allows the test engineers to discover and resolve possible conflicts between these components.
One drawback to the forgoing hardware-based test procedure, however, is that it is quite costly to implement. This is because the hardware-based test procedure requires repeated adjustments in parameter settings and repeated replacements of hardware devices, which makes the procedure quite laborious and time-consuming to carry out.
Still another drawback to the hardware-based test procedure is that it can be carried out only after the tape-out of the components. If a component is judged to be defective, it will be discarded and then redesigned. This practice, however, makes the overall manufacture quite cost-ineffective. The hardware-based test procedure is therefore highly undesirable.
In summary, the prior art has the following drawbacks.
First, the testing of each of the various components through a specifically designed test procedure is less likely to discover those problems that will arise from the conflicts between these components when they operate together. If these conflicts are not resolved by the testing, they might cause the computer system to crash during real operations. Second, the hardware-based test procedure is quite laborious and time-consuming to carry out, and is therefore quite costly to implement.
SUMMARY OF THE INVENTION
It is therefore the primary objective of this invention to provide an integrated testing method, which is capable of concurrently performing a test procedure on a number of components, which test procedure is performed in a multitasking manner through software simulation.
It is another objective of this invention to provide an integrated testing method which can be performed before the tape-out of the components so that the overall manufacture process can be made more cost-effective than the prior art.
In accordance with the foregoing and other objectives, the invention proposes an integrated testing method for performing a test procedure on a number of components concurrently in a multitasking manner through software simulation.
The integrated testing method of the invention includes the following steps: specifying a total number of simulated operations for the testing of the components under test; specifying a FIFO buffer size for the components under test; generating a command sequence including a number of commands based on a first specified random number range, with each command being used to simulate a certain task; generating a start time of operation based on a second specified random number range; concurrently activating all the components under test to operate in response to each command from the command sequence; and in the event that at least two of the components under test are competing for the same resource, activating an arbiter to perform arbitration for these competing components.
The components under test include, for example, a DMA (Direct Memory Access) component, an SIO (Super Input/Output) component, an ISA (Industry Standard Architecture) component, an AC (Audio Codec) component, a USB (Universal Serial Bus) component, an IDE (Integrated Device Electronics) component, an AGP (Accelerated Graphic Port) component, a PCI (Peripheral Component Interconnect) component, and a CPU (Central Processing Unit). The arbiter can be either a South Bridge chipset or a North Bridge chipset.
The integrated testing method of the invention allows the test procedure to be performed concurrently in a multitasking manner on all the components through software simulation, which is more efficient than the prior art. Moreover, the invention allows the test procedure to be less laborious and time-consuming, and is therefore more cost-effective to implement than the prior art.
REFERENCES:
patent: 4236246 (1980-11-01), Skilling
patent: 5088024 (1992-02-01), Vernon et al.
patent: 5274774 (1993-12-01), Manber et al.
patent: 5488573 (1996-01-01), Brown et al.
patent: 5548785 (1996-08-01), Fogg et al.
patent: 5881270 (1999-03-01), Worthington et al.
patent: 6002854 (1999-12-01), Lynch et al.
patent: 6018807 (2000-01-01), Larson
patent: 6405326 (2002-06-01), Azagury et al.
patent: 6484281 (2002-11-01), Wang et al.
patent: 6507809 (2003-01-01), Yoshino et al.
patent: 6535841 (2003-03-01), Meyer
patent: 6637019 (2003-10-01), Rinaldi
Chang Nai-Shung
Huang Hsiang-Chou
Lai Jiin
J.C. Patents
Maskulinski Michael
VIA Technologies Inc.
LandOfFree
Integrated testing method for concurrent testing of a number... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated testing method for concurrent testing of a number..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated testing method for concurrent testing of a number... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3280248