Method for forming integrated dielectric layers

Details Method for forming integrated dielectric layers Method for forming integrated dielectric layers

2002-10-30

2004-11-09

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S970000, C438S624000, C438S780000

Reexamination Certificate

active

06815332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods of forming integrated dielectric layers which may be used in semiconductor devices, and particularly relates to methods that involve formation of etch-stop layers using a CVD apparatus.
2. Description of the Related Art
Semiconductor devices include metal layers that are insulated from each other by dielectric layers. As device features shrink, a reduction of the distance between the metal layers increases. To achieve this task, a low dielectric film is introduced to replace the conventional silicon dioxide films and other materials having a relatively high dielectric constant to form a dielectric layer that separates the metal lines, i.e., metal layers.
A material that may be considered suitable for such a task includes a carbon-doped silicon dioxide film. Using this material to divide the metal lines may yield a device having a reduced propagation delay, cross-talk noise, and power dissipation. Although this film appears to be perfect for replacing silicon dioxide films, there are other film properties that may not be comparable to silicon dioxide films. That includes, for instance, elastic modulus and hardness. Most carbon-doped films have less than 14% of silicon dioxide elastic modulus and 20% of silicon dioxide hardness. These may lead to a severe problem when the wafer is subjected to subsequent processes such as chemical mechanical polishing (CMP) and packaging involving long-standing integration issues.
Accordingly, there is a need for films having high modulus and hardness to circumvent the long-standing integration issues. The conventional schemes of so called “no etch-stop integration” have not been very successful due to the occurrence of strong attack on the corners of via holes during a subsequent metal trench etch process.
Various damascene methods have been reported in the field of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties. For example, the damascene methods include, but are not limited to, the damascene methods disclosed in the following, the disclosure of which is incorporated herein by reference in its entirety:
(1) U.S. Pat. No. 6,100,184 to Zhao et al., teaching a dual damascene method for forming a copper-containing contiguous patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer formed with a comparatively low dielectric constant dielectric material, thereby contacting a copper-containing conductor layer formed thereunder, wherein a conductor barrier/etch-stop layer is used to selectively passivate only the top surface of the copper-containing conductor layer formed thereunder;
(2) U.S. Pat. No. 6,140,226 Zhao et al. teaching a dual damascene method for forming a contiguous patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed with a comparatively low dielectric constant dielectric material wherein a sidewall liner layer is used for the purposes of protecting a sidewall of the trench from lateral etching when contiguously forming the via therewith;
(3) U.S. Pat. No. 6,177,364 to Huang teaching a dual damascene method for forming a contiguous patterned conductor interconnect and a patterned conductor stud layer within a corresponding trench contiguous with a corresponding via through a dielectric layer formed with a comparatively low dielectric constant fluorosilicate glass (FSG) dielectric material wherein a hydrogen-nitrogen plasma treatment is employed for the purposes of passivating a sidewall surface of the dielectric layer within the corresponding trench contiguous with the corresponding via prior to forming therein the contiguous patterned conductor interconnect and patterned conductor stud layer; and
(4) U.S. Pat. No. 6,211,092 to Tang et al. teaching a counterbore type dielectric etch method which may be employed when forming through a dielectric layer a dual damascene aperture for a dual damascene method, wherein the counterbore type dielectric etch method uses a plurality of etch steps when first forming a via through the dielectric layer.
In the field of microelectronic fabrication, desirable are additional damascene methods and materials which can be employed for providing patterned microelectronic conductor layers each interposed between microelectronic dielectric layers formed with comparatively low dielectric constant dielectric materials, thereby attenuating damage to the microelectronic dielectric layers.
All low-dielectric constant films that are currently available on the market are manufactured accordingly and have an elastic modulus of lower than 10 GPa as measured by Diamond indentation methods (e.g., by a Nano-indenter manufactured by MTS).
An object of the present invention is to provide a method and a film having great advantages over the conventional methods and films with respect to subsequent processes such as CMP and Packaging.
The conventional integration methods are further explained below. In implementing conventional dual damascene techniques wherein a via is formed before a trench, an etch-stop layer is formed on and under a first dielectric layer which overlies a capped metal feature. The etch-stop layer is typically formed with silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, which is chosen for its high etch selectivity with respect to an overlying second dielectric layer which is then deposited on the etch-stop layer. Thus, the second dielectric layer is deposited on the upper etch-stop layer. A photoresist mask is then formed over the second dielectric layer, and anisotropic etching is conducted to form a via through the first and second dielectric layers and stops on the lower etch-stop layer. Subsequently, a trench pattern is formed on the second dielectric with a barrier anti-reflective coating (BARC) filling the via (Conformal and Planarization). Trench anisotropic etching is conducted to form a trench and stops on the upper etch-stop layer (which is under, the second dielectric layer and thus is referred to as an “intermediate” etch-stop layer). Finally, the photoresist is removed with a conventional ashing process, and then copper metallization is commenced.
As miniaturization proceeds apace with attendant shrinkage in the size of metal lines, e.g., the width of a metal line is about 0.25 micron or lower, or about 0.1 micron or lower, the ILD dielectric constant of the interlining material is very important. This includes the dielectric constant of the etch-stop layer. Accordingly, there is the need for an interconnection methodology enabling the formation of metal features, such as metal lines, with high dimensional accuracy and low effective k-value.
The present invention provides solutions to these complicated integration problems.
SUMMARY OF THE INVENTION
In an aspect of the present invention, a method is provided to form on a substrate a laminated structure including a layer-to-be-etched and an etch-stop layer. In an embodiment, the method comprises the steps of: (i) introducing into a reactor a reaction gas comprised of a source gas containing silicon and carbon at a source gas flow rate and an inert gas at an inert gas flow rate which is 40% or higher of the source gas flow rate; (ii) applying plasma energy to a space where the reaction gas is present upstream of a substrate mounted on a heated substrate-supporting member; (iii) forming an etch-stop layer on the substrate from the reaction gas with plasma energy; and (iv) forming a laminated structure by forming at least one layer-to-be-etched on the substrate. In the above, the laminated structure may be a dual damascene structure.
The source gas may be Si
&agr;
O
&agr;−1
R
2&agr;−&bgr;+2
(OC
n
H
2n+1
) wherein &agr; is an integer of 1-3, &bgr; is an integer of 1-3, n is an integer of 1-3, and R is C
1-6
hydroca

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