Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-25
2004-08-10
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000
Reexamination Certificate
active
06774431
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory cells.
BACKGROUND OF THE INVENTION
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories.
The non-volatile memory cells are fabricated as floating gate memory cells and include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and is can also made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is “floating” in dielectric so that it is insulated from both the channel and the control gate.
As semiconductor devices get smaller in size, designers are faced with problems associated with the production of memory cells that consume a small enough amount of surface area to meet design criteria, yet maintain sufficient performance in spite of this smaller size. In the DRAM art, one type of memory cell capacitor that has proven successful in this regard is the container capacitor, which is so named for its container-like appearance. The capacitor has a bottom electrode that is fabricated to resemble a container having upwardly extending sidewalls to define a central recess, or opening. A layer of dielectric is formed over the bottom electrode and then a top electrode is fabricated over the dielectric. The amount of capacitive between the electrodes, coupling per die area, is substantially increased over non-container capacitors.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory cell that can be reduced to occupy less die area and maintain operating performance.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a transistor comprises a substrate, source and drain regions located in the substrate and laterally spaced apart to define a channel region, and a floating gate located above the channel region. The floating gate comprises a first portion extending in a general horizontal direction, and a second portion extending in a general vertical direction. A control gate is located adjacent to the second portion.
In another embodiment, a transistor comprises a substrate, source and drain regions located in the substrate and laterally spaced apart to define a channel region, and a floating gate located above the channel region. The floating gate comprises a vertically extending container having interior and exterior regions. A control gate is located adjacent to the container.
A floating gate transistor of another embodiment comprises a source, a drain, a horizontally extending channel region between the source and drain, and a control gate. A floating gate is located above the channel region, wherein a primary coupling surface of the floating gate to the control gate extends in a substantially vertical direction.
A method of fabricating a floating gate transistor comprises fabricating laterally spaced source and drain regions to define a channel therebetween, fabricating a first layer of oxide over the channel, and fabricating a semiconductive first floating gate portion laterally extending over the first layer of oxide and above the channel. A vertically extending semiconductive contact is fabricated to couple to the first floating gate portion. The method further comprises fabricating a vertically extending semiconductive container coupled to the contact, fabricating a second layer of oxide over the container, and fabricating a control gate over the second layer of oxide to provide electrical coupling to the container.
REFERENCES:
patent: 4864464 (1989-09-01), Gonzalez
patent: 5192872 (1993-03-01), Lee
patent: 5354705 (1994-10-01), Mathews et al.
patent: 5444279 (1995-08-01), Lee
patent: 5729496 (1998-03-01), Jung
patent: 5732014 (1998-03-01), Forbes
patent: 5897351 (1999-04-01), Forbes
patent: 5914511 (1999-06-01), Noble
patent: 5932910 (1999-08-01), Hong
patent: 5965913 (1999-10-01), Yuan et al.
patent: 5981335 (1999-11-01), Chi
patent: 6066869 (2000-05-01), Noble
patent: 6156607 (2000-12-01), Noble
patent: 6172394 (2001-01-01), Nakagawa
patent: 6272047 (2001-08-01), Mihnea
patent: 6297989 (2001-10-01), Cloud
patent: 6323085 (2001-11-01), Sandhu
patent: 6323514 (2001-11-01), Kao
patent: 6373095 (2002-04-01), Bracchitta et al.
patent: 6384447 (2002-05-01), Mihnea
patent: 6413818 (2002-07-01), Huang et al.
patent: 6448615 (2002-09-01), Forbes
patent: 6461915 (2002-10-01), Rudeck
patent: 2002/0079523 (2002-06-01), Zheng
Leffert Jay & Polglaze P.A.
Ngo Ngan V.
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