Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-09-23
2004-03-16
Clark, Sheila V. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S697000
Reexamination Certificate
active
06707142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to stacking technology of semiconductor package devices, and more particularly, a package stacked semiconductor device having pin linking means for operating a plurality of package devices as a single semiconductor device.
2. Description of the Related Art
One of methods to improve capacity of a semiconductor IC (Integrated Circuit) device is stacking several chips or packages into a single device. The stacking of IC devices is necessary as well for improving mounting density required as the chip size increases according to the improvement in density and performance of the IC devices. The stacked semiconductor device can be divided into: a chip stacked device in which unpackaged bare chips are stacked, and a package stacked device with assembled package devices being stacked.
In the conventional package stacked semiconductor device, e.g., as disclosed in U.S. Pat. No. 5,313,096, a number of packages are stacked vertically on a lead frame and electrode pads of the upper and lower packages are electrically interconnected by a solder strip, or as disclosed in U.S. Pat. No. 5,978,227, an intermediate lead frame or PCB is provided between upper and lower packages for the electrical interconnection of the upper and lower packages with the first terminals of the intermediate lead frame being connected to outer leads of the upper package and the second terminals of the intermediate lead frame being connected to outer leads of the lower package.
The conventional device requires additional components such as a solder strip or an intermediate lead frame for stacking packages. Conventional package stacked device shown in
FIG. 1
has the additional components within individual package device.
FIG. 1
shows the structure disclosed in U.S. Pat. No. 6,242,285 entitled “Stacked Package of Semiconductor Package Units Via Direct Connection Between Leads and Stacking Method Therefor”, in which leads PI
A
, PI
B
, . . . of upper and lower packages IC
B
and IC
A
are directly connected in one-to-one fashion. For operation of the stacked package, the length of a part of leads i.e., a lead P
19
B
of the upper package IC
B
is shortened to be disconnected from corresponding lead P
19
A
of the lower package. The P
19
B
lead is electrically interconnected to P
15
A
lead of the lower package through an additional component within the package. The electrical connection between leads P
19
A
and P
15
A
may be formed either through the modification of lead frame structure where a bus bar lead
419
B
is modified to directly connect CS lead
15
and an external NC lead
19
of the upper package IC
B
as shown in
FIG. 1
b
or through ajump wire
319
JP
B
connecting the CS lead
15
and the external NC lead
19
as shown in
FIG. 1
c
. The jump wire
319
JP
B
is different from the wires
312
B
and
319
B
connecting leads and chip electrode pads in that it connects the leads.
The conventional stacked package device using the direct stacking technology (DST) has an advantage that memory capacity of a memory module can be improved without special consideration of the design.
However, the conventional stacked devices require the modifications of internal structure (e.g., lead frame leads) or additional bonding wires (e.g., the jumper wires). Further, the conventional stacked device where the additional structure is formed externally to the package entails the increase of costs and results in complexity of processing step for introducing solder strips and intermediate lead frame.
SUMMARY OF THE INVENTION
It is an object of this invention to implement more simply and more easily a package stacked semiconductor device.
Other object of this invention is to provide a simple manufacturing process of package stacked semiconductor devices with an increased productivity.
According to one aspect of this invention, a package stacked semiconductor device is implemented by stacking upper and lower packages, each having a semiconductor IC chip with a plurality of electrode pads on its active surface, a plurality of conductive leads for electrically connecting the electrode pads to external devices, and a package body for encapsulating the semiconductor chip and parts of the leads. The conductive leads include power pins, data pins for inputting and outputting to and from the semiconductor IC chip, control signal pins and NC pins. The stacked device includes a plurality of pin connection parts for electrically connecting the conductive leads of the upper package to the respective corresponding conductive leads of the lower package. The plurality of conductive leads of the upper package include at least one control signal pin connected to neighboring NC pin by a pin linking means instead of the pin connection parts. The at least one control pin is electrically interconnected to an NC pin of the lower package, which corresponds to the neighboring NC pin of the upper package.
In the present invention, the pin linking means can be implemented by a jumper having a central perforated part (or a through hole), a jumper means having opening at both sides of conductive body, a jumper having one or two parallel through grooves, and a ribbon wire connected to inner leads. The pin linking means can be formed by re-forming or bending the at least one control signal pin to directly contact the neighboring NC pin of the upper package.
According to other aspect of the present invention, a package stacked semiconductor device comprising: an upper package and a lower package, each having a semiconductor chip provided with a plurality of electrode pads, a plurality of conductive leads for electrically connecting the electrode pads to external world and a package body for encapsulating the semiconductor chip and a part of the conductive leads; the plurality of conductive leads including power pins for power signal for the semiconductor chips, data pins for inputting and outputting data to and from the semiconductor chips, control signal pins and extra no connection (NC) pins; a plurality of pin connection parts for directly connecting the plurality of conductive leads of the upper and lower packages by the power pins, data pins and control signal pins; and the plurality of conductive leads of the upper package including at least one control pin connected to neighboring NC pin by a dam bar, one of the at least one control pin and the neighboring NC pin having a shortened length to be disconnected from a corresponding pin of the lower package, and the other of the at least one control pin and the neighboring NC pin being directly and electrically connected to a corresponding pin of the lower package. The at least one control signal pin is made shortened to be disconnected from the NC pin of the lower package that corresponds to the neighboring NC pin of the upper package.
In one embodiment of the present invention, by using a bridge lead formed at a distant location from a dam bar of the upper package toward the outer leads, an NC pin of the upper package can be electrically interconnected to neighboring control pin.
REFERENCES:
patent: 4398235 (1983-08-01), Lutz et al.
patent: 6462408 (2002-10-01), Wehrly, Jr.
patent: 6572387 (2003-06-01), Burns et al.
Choi Wan-Gyun
Jeong Do-Soo
Barun Electronics Co., Ltd.
Bushnell , Esq. Robert E.
Clark Sheila V.
LandOfFree
Package stacked semiconductor device having pin linking means does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Package stacked semiconductor device having pin linking means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Package stacked semiconductor device having pin linking means will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3279447