CMOS clock drivers with inductive coupling

Details CMOS clock drivers with inductive coupling CMOS clock drivers with inductive coupling

1995-01-13

1996-04-16

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 98, 326 83, H03K 19096

Patent

active

055086390

ABSTRACT:
The invention is a power conserving clock driver circuit operative where a differential pair of clock (clock+ and clock-) signals are desired. The circuit responds to transitions in both clock signals to turn off the clock driver transistors (M1P,M1N) (M2N, M2P) for a period of time. During that period of time, a pass gate configuration (M3N, M3P) is conductive. When this occurs, the charge on one of the capacitive loads C.sub.L1 or C.sub.L2 is transferred through the inductor L.sub.c. In this fashion, part of the charge on one of the capacitive loads is transferred directly to the other capacitive load thereby conserving power. The time period during which this power transfer occurs is the time for one half cycle at the natural resonant frequency of the circuit comprised of L.sub.c, C.sub.L1 and C.sub.L2.

REFERENCES:
Seitz et al.; "Hot Clock nMOS"; paper delivered at the 1985 Chapel Hill Conference on VLSI; pp. 1-17, Computer Science Press, 1985.
Koller et al.; "Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information"; Aug. 1992; pp. 1.5.
Merkle; "Reversible Electronic Logic Using Switches"; .COPYRGT.1990 by Xerox Corporation; published Sep. 1992, pp. 1-31.
Younis et al.; "Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS"; Oct. 1992; pp. 1-15.

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