Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-15
2004-02-17
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S624000, C438S626000, C438S754000
Reexamination Certificate
active
06693028
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-183194, filed Jun. 19, 2000; and No. 2001-138681, filed May 9, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a multilayer wiring structure using copper and a method for manufacturing the semiconductor device.
Recently a semiconductor device with a dual-damascene structure has been provided in which copper wiring is employed as a multilayer-wiring layer.
FIGS. 22
to
26
are cross-sectional views each showing a prior art step of manufacturing a semiconductor device. A method for forming copper wiring in a dual-damascene structure will be described below with reference to
FIGS. 22
to
26
.
As shown in
FIG. 22
, a first wiring groove
62
is first formed in a first insulating film
61
and then a conductive film
63
a
such as a copper film is formed on the first insulating film
61
by electrolytic plating, with the result that the first wiring groove
62
is filled with the conductive film
63
a
. The conductive film
63
a
is flattened by CMP (Chemical Mechanical Polishing) and the surface of the first insulating film
61
is exposed. Consequently, a first wiring layer
63
is formed in the first insulating film
61
.
As illustrated in
FIG. 23
, a second insulating film
64
is formed on the first insulating film
61
and the first wiring layer
63
. A via hole
65
and a second wiring groove
66
are formed in the second insulating film
64
by lithography and dry etching.
Referring to
FIG. 24
, a barrier metal layer
67
having a thickness of 200 Å is formed on the second insulating film
64
and the first wiring layer
63
, and a metal seed layer (not shown) having a thickness of 400 Å is formed on the barrier metal layer
67
. Then, a conductive film
68
is formed on the metal seed layer by electrolytic plating, and the via hole
65
and second wiring groove
66
are filled with the conductive film
68
.
As shown in
FIG. 25
, the conductive film
68
, metal seed layer, and barrier metal layer
67
are flattened by CMP to expose the surface of the second insulating film
64
. As a result, a via section
69
and a second wiring layer
70
that are electrically connected to the first wiring
63
are formed.
However, the via hole
65
decreases in size in accordance with miniaturization of elements and thus the conductive film
68
cannot sufficiently be buried into the via hole
65
from top to bottom. As a result, a void
71
is formed in the via hole
65
to cause faulty electrical continuity between the first wiring
69
and the via section
69
, as illustrated in FIG.
26
. If the opening of the via section
69
is smaller than the second wiring layer
70
, the conductive film
68
becomes more difficult to bury. The void
71
is therefore easily formed in the via hole
65
to make a problem of the faulty electrical continuity more serious.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in order to resolve the above problem. An object of the present invention is to provide a semiconductor device capable of avoiding faulty electrical continuity between wiring and a via section, and a method for manufacturing the semiconductor device.
In order to attain the above object, the present invention employs the following means:
A method for manufacturing a semiconductor device according to a first aspect of the present invention, comprises the steps of forming a first insulating film;
forming a first groove in the first insulating film; forming a conductive film in the first groove; selectively forming a second insulating film on the conductive film and the first insulating film, the second insulating film being formed so as to form a first region in which the second insulating film covers a surface of the conductive film and a second region in which the second insulating film does not cover the surface of the conductive film; forming a second groove by removing part of the conductive film of the second region using the second insulating film as a mask, the second groove being formed so as to form a connecting portion of the conductive film under the second insulating film and form a first wiring layer by forming the connecting portion with a bottom of the first groove integrally with each other as one unit; removing the second insulating film; forming a third insulating film in the second groove; and forming a second wiring layer electrically connected to the first wiring layer through the connecting portion.
The method according to the first aspect further comprises the steps of forming the third insulating film on the second insulating film and in the second groove, leaving the second insulating film, after the connecting portion and the first wiring layer are formed; removing the third insulating film until a surface of the second insulating film is exposed; removing the third insulating film such that the second groove and a periphery of the second insulating film are filled with the third insulating film; forming a third groove in the third insulating film so as to expose a surface of the connecting portion by removing the second insulating film with the exposed surface; and forming the second wiring layer in the third groove.
A method for manufacturing a semiconductor device according to a second aspect of the present invention, comprises the steps of forming a first insulating film; forming a second insulating film on the first insulating film; forming a third insulating film on the second insulating film; forming a first groove in the first, second and third insulating films; forming a conductive film in the first groove; selectively forming a fourth insulating film on the conductive film and the third insulating film, the fourth insulating film being selectively formed so as to form a first region in which the fourth insulating film covers a surface of the conductive film and a second region in which the fourth insulating film does not cover the surface of the conductive film; removing the conductive film of the second region using the fourth insulating film as a mask, the conductive film being removed so as to form a connecting portion of the conductive film under the fourth insulating film and form a first wiring layer by forming the connecting portion with a bottom of the first groove integrally with each other as one unit; removing the third and fourth insulating films to expose a surface of the second insulating film; forming a fifth insulating film on the second insulating film with the exposed surface and on the first wiring layer; and forming a second wiring layer electrically connected to the first wiring layer through the connecting portion.
A semiconductor device according to a third aspect of the present invention comprises a first wiring layer; a second wiring layer formed above the first wiring layer; and a connecting portion for electrically connecting the first and second wiring layers, the connecting portion being formed integrally with the first wiring layer as one unit, and a boundary between a side of the connecting portion and a surface of the first wiring layer being curved.
In the semiconductor device according to the third aspect, the surface of the first wiring layer and the side of the connecting portion are removed by wet etching. The connecting portion has an opening with dimensions smaller than minimum process dimensions.
According to the semiconductor device and its manufacturing method described above, faulty electrical continuity between the wiring layer and the via section can be avoided.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations partic
Frommer & Lawrence & Haug LLP
Kabushiki Kaisha Toshiba
Pham Thanhha
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