On-chip debugging system emulator

Details On-chip debugging system emulator On-chip debugging system emulator

2000-11-30

2004-02-10

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S040000, C703S027000

Reexamination Certificate

active

06691251

ABSTRACT:

FIELD OF THE INVENTION
The disclosure relates to an on-chip debugging system emulator. Further, the disclosure relates to an on-chip debugging system emulator in which a computer program is configured to run on the processor of a computing device and is configured to emulate the on-chip debugging functions of a silicon chip having an on-chip debugging system.
BACKGROUND OF THE INVENTION
Processor vendors, selling silicon chip devices, have provided on-chip debugging (OCD) circuitry to improve the process of high-end embedded processor development. In general, on-chip debugging is a combination of hardware and software, both on and off the chip. The portion which resides on the chip may be implemented in various ways. For example, it may be a microcode based monitor (Motorola CPU 32, e.g.) or hardware implemented resources (IBM PPC403, e.g.). Further, there may be resources used that are available to the end-user's code such as breakpoint registers (most embedded power PC implementations, e.g.) or dedicated hardware purely used by the OCD such as instruction stuff buffers (also in embedded power PC implementations, e.g.).
An exemplary prior art OCD system emulation solution uses field programmable gate arrays (FPGAs). The circuit or chip design to be emulated is realized on the FPGA emulation system by compiling a “formal” description of the circuit design, and mapping the circuit design out of the logic elements of the FPGA.
On-chip debugging requires some external hardware. For example, there must be a communications interface between the chip and the debugger host. In most cases this is via a dual-row pin header and several pins on the processor. For example,
FIG. 1
depicts a system
100
of the prior art. On-chip debugging system
100
includes an on-chip debugging host computer
110
coupled to and in communication with an on-chip debugging interface hardware
120
which may be a Joint Test Action Group (JTAG) interface, that is an interface configured to utilize the IEEE 1149.1 JTAG test instruction standard.
JTAG is an IEEE specification (IEEE 1149.1). JTAG is a method for doing full chip testing and was originally implemented to allow testing of all the pin connections of a chip and its interconnections to other chips on a circuit board. JTAG is a serial protocol and chips on the board may be daisy-chained together. The JTAG serial chain through the chip may be wired through any on-chip devices but typically minimally connects to all the I/O pins and buffers.
In on-chip debugging devices, using the IEEE 1149.1 JTAG test instruction set, host computer
110
is typically connected to interface
120
that translates from signals that the host computer
110
understands to an interface and signals that a silicon chip
130
can understand, and host computer
110
provides the ability to query and set information within microchip
130
. This on-chip debugging ability is useful when developing software for or programming for a silicon chip or other processing device.
OCD interface hardware
120
is coupled to and in communication with a silicon chip device or processor
130
having OCD resources (hardware and software, e.g.)
135
dedicated to on-chip debugging processes. OCD interface
120
in many cases uses a dual-row pin header and several pins on the processor to communicate between OCD host computer
110
and processor
130
. For example, the IBM 403 family uses the JTAG port pins, in addition to RESET, power sense and ground, and connects via a 16-pin dual-row header. Motorola background debug mode (BDM) typically uses five dedicated pins (sometimes multiplexed with real-time execution functions), power, ground, and at least one RESET, all terminating in a 10-pin dual-row header. Many of the DSP chips use a Texas Instrument style standard JTAG interface. Motorola further, has expanded the interface's internal definition to include its DSP BDM equivalent (referred to as OnCE). However, other hardware interface architectures may be used.
To provide debugging of processor
130
, OCD host computer
110
is also required. The host computer
110
runs the debugger software and interfaces to the OCD header in various ways. The debugger on OCD host computer
110
implements the user interface displaying, for example, the program code for processor
130
, processor resources, target memory, etc. The hardware interface
115
between OCD host computer
110
and OCD interface hardware
120
may be any of a variety of types, including, RS-232, high speed parallel ports, ethernet, ISA bus interfaces, etc.
Companies developing software and hardware tools to debug microchips, such as processor
130
and other microchips and silicon chips such as through the IEEE 1149.1 JTAG test instruction set, or other instruction sets, are often posed with the problem of having to develop software and hardware for a microchip that does not yet exist, or is unavailable.
Accordingly, there is a need for an emulator which mimics the functionality of the debugging portion, for example OCD
135
, of the microchip, thereby allowing the software or hardware vendors to develop their products for chips which do not yet exist or are unavailable.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to an on-chip debugging system emulator. The on-chip debugging system emulator includes an on-chip debugging host processor. The on-chip debugging system emulator also includes an on-chip debugging emulator processor configured to emulate the on-chip debugging functions of a silicon chip. Further, the on-chip debugging system emulator includes a hardware interface between the on-chip debugging host processor and the on-chip debugging emulator processor.
Another exemplary embodiment relates to an on-chip debugging system emulator. The on-chip debugging system emulator includes an on-chip debugging host processor running software to display on-chip debugging emulation information. The on-chip debugging system emulator also includes an on-chip debugging emulator processor running software to emulate the on-chip debugging functions of a silicon chip. Further, the on-chip debugging system emulator includes a hardware interface between the on-chip debugging host processor and the on-chip debugging emulator processor.
Yet another exemplary embodiment relates to an on-chip debugging emulator. The on-chip debugging emulator includes a processor and a memory device coupled to the processor. The on-chip debugging emulator also includes an interface coupled to the processor, the interface configured to be coupled to an on-chip debugging host device. Further, the on-chip debugging emulator includes a software program configured to run on the processor and configured to emulate the on-chip debugging functions of a silicon chip.


REFERENCES:
patent: 5754827 (1998-05-01), Barbier et al.
patent: 6480952 (2002-11-01), Gorishek et al.
patent: 6516428 (2003-02-01), Wenzel et al.
patent: 6557116 (2003-04-01), Swoboda et al.
patent: 2002/0059542 (2002-05-01), Debling
Rick Leatherman. “On-Chip Instrumentation Approach to System-On-Chip Development”.http://www.fs2.com/pdfs/OCI_Whitepaper.pdf.Jul. 22, 2000.*
“System verification: essential for digital wireless system-on-chip (SOC) designs”. http://www.eetasia,com/ARTICLES/1999SEP/1999SEP09_ST_SMT_TAC.PDF. 1999.*
“Cut Based Functional Debugging for Programmable Systems-on-Chip” IEEE. Feb. 2000.*
Nath, Manju, “On-Chip Debugging Reaches A Nexus”,techtrends, May 11, 2000, pps. 95-96, 98 and 100.
Haller, Craig A., “The ZEN of BDM,” © Copyright 1996-97 Macraigor Systems, Inc., pps. 1-15.
Neugass, Henry, “Approaches to on-chip debugging,”Computer Design, Dec. 1998, pps. 1-11; printed from the following website: www.computer-design.com/Editorial/1998/12/TDP/decdebug.html on Nov. 9, 2000.
ARM7DMI Data Sheet, Document No.: ARM DDI 0029E, Issued: Aug. 1995, © Advanced RISC Machines Ltd. (ARM) 1995, Table of Contents and Sec. 8.1 entitled “Debug Interface,” pps. i-v and 8-2 to 8-30.
Young, Johnny, “JTAG/IEEE 1149.1—Design Considerations,” Application Report, pps. i-iv and 1-11, © 1996

Affiliated with

Also associated with

Rating

On-chip debugging system emulator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip debugging system emulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip debugging system emulator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3277218