Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-06
2004-12-14
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S302000
Reexamination Certificate
active
06831322
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, more specifically to a semiconductor memory device and a method for fabricating the same which can fabricate a DRAM (Dynamic Random Access Memory) of high integration and high efficiency at low costs.
A DRAM is a semiconductor device which may comprise one transistor and one capacitor, and its structures and methods for fabricating the structures have been conventionally studied for fabricating semiconductor devices of high density, high integration and high efficiency.
To achieve higher integration of a DRAM, it is effective to make the capacitor area smaller. The capacitance reduction accompanies soft error resistance degradation. This is a disadvantage. Lower electric power consumption of the device as well as higher integration has achieved, but the electric power consumption reduction makes the junction capacitance of the device more influential, which is a barrier to higher speed operation of the device.
As effective means to solve these disadvantages, a method for fabricating a DRAM using an SOI (Semiconductor On Insulator) substrate in place of the conventional silicon substrate has been proposed.
By applying the SOI structure to a DRAM, perfect isolation between devices can be made possible, and the soft error immunity and latch-up resistance can be much improved. The junction area can be reduced, and high speed operation at low electric power consumption can be made possible. Furthermore, the soft error immunity can be thus improved, which allows a smaller capacitance. The capacitor forming process can be accordingly simplified.
Also proposed has been the so-called bonded SOI technique in which another substrate is adhered to a surface of a silicon substrate with an insulating portion formed on, which is on the side of the insulating portion, and the silicon substrate is polished to form a semiconductor layer on the insulating portion. A DRAM using this bonded SOI technique is disclosed in Japanese Patent Laid-Open Publication No. Tokkaihei 04-225276/1992 and Japanese Patent Laid-Open Publication No. Tokkaihei 06-104410/1994.
The DRAM using the above-described conventional SOI structure can simplify the capacitor forming process to thereby decrease costs, but cost increase due to the use of the SOI structure exceeds the cost decrease, sometimes with the result of higher fabrication costs.
In devices using the above-described conventional SOI structure, the devices are fabricated after the SOI substrate is formed. The substrate is subjected to all heat treatments for forming the devices. Because SOI substrates are usually more susceptible of heat treatments than the usual substrates, the wafers are easily deformed, and crystal defects are easily introduced. As a result, the fabrication yields are often low.
In the DRAM using the above-described SOI structure, for the purpose of reducing this disadvantage as much as possible, a material having a thermal diffusion coefficient equal to that of the SOI layer supported on the support substrate, e.g., a semiconductor substrate of the same single crystal as the SOI layer, must be used. This often adds to fabrication costs of the DRAM.
In the bonded SOI, devices are formed on the SOI layer which is adhered thereto the substrate and polished. Accordingly it is necessary to finish the polished surface in a speculum of high precision. The polishing step often adds to fabrication costs.
To form the usual SOI substrate, the polishing step of planarizing a surface of a semiconductor substrate before the substrate is adhered to, and the polishing step of polishing the adhered semiconductor substrate to a thin film to form the SOI layer are necessary. This often adds to fabrication costs.
The use of the SOI structure makes it difficult to apply back bias to the channel regions of transistors, and the source-drain voltage resistance is often degraded due to charges accumulated in the back gates.
To prevent erroneous operation of memories, it is effective to cover the bit lines with shield electrodes. In the conventional DRAM structure, however, a number of lines and capacitors are formed on the bit line, which makes it difficult to cover the bit lines with the shield electrodes.
The above-described disadvantages make it difficult to form memories of high soft error immunity and reliability, which makes it accordingly difficult to reduce the capacitance to thereby simplify the fabrication process.
An object of the present invention is to provide a semiconductor memory device structure which permits a semiconductor memory device including the SOI structure to be fabricated at low costs without fabrication yield decrease, and a method for fabricating the same.
SUMMARY OF THE INVENTION
The above-described object is achieved by a semiconductor memory device comprising: a silicon layer having a first diffused region and a second diffused region formed therein; a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions; a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region; and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated.
The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.
The above-described object is also achieved by a semiconductor memory device comprising: a silicon layer having a first diffused region and a second diffused region formed therein; a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions; a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region; a bit line formed on said one side of the silicon layer and connected to the second diffused region; and a strapping word line formed on the other side of the silicon layer and connected to the gate electrode, whereby a semiconductor memory device of SOI structure can be easily fabricated.
In the above-described semiconductor memory device it is preferable that a connection surface of the storage electrode, which are connected to the first diffused region, is substantially parallel with a surface of the storage electrode, which correspond to the connection surface, whereby a DRAM process and an SOI process can be easily unified.
The object of the present invention can be achieved by the semiconductor memory device comprising a semiconductor memory device comprising: a device layer including a semiconductor layer having a first diffused region and a second diffused region formed therein, a transistor having a gate electrode formed through an insulation film on one side of the semiconductor layer between the first and the second diffused regions, and a capacitor formed on said one side of the semiconductor layer and having a storage electrode connected to the first diffused region; a bit line formed on the other side of the semiconductor layer, and extended in a direction normal to the gate electrode; and a support substrate formed on said one side of the semiconductor layer for supporting the device layer; the semiconductor layer including a first region which is extended in the direction of extension of the bit line and includes the first diffused region and the second diffused region, and a second region which is extended in a direction of extension of the gate electrode in the first region and includes the second diffused region; a first contact hole being formed in the first region for connecting the first diffused region to the capacitor; and a second contact hole being formed in the second region for connecting the bit line with the second
Fujitsu Limited
Nadav Ori
Westerman Hattori Daniels & Adrian LLP
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