Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2002-01-08
2004-03-09
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S686000, C257S691000, C257S700000
Reexamination Certificate
active
06703706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the manufacture of electronic packages, and more particularly to methods and apparatus for optimization of an electronic package. In particular, the present invention relates to optimization of a plurality of wiring solutions for an electronic package.
2. Related Art
In a conventional multilayer semiconductor electronic package, such as, inter alia, an Application Specific (ASIC) chip package, or a printed circuit board, a variety of electrical signals are transmitted. Each type of electrical signal is best handled by wires with certain electrical parameters, such as, inter alia, resistance, characteristic impedance, electromagnetic coupling, and whether a single wire or a wire pair is used.
These electrical parameters are usually optimized independently, within each of one or more layers, leading to either more expensive packages with more layers, or leading to the impossible task of accommodating conflicting requirements when the number of layers is limited.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to overcome the above shortcomings related to optimizing electrical parameters related to signal wiring, by providing a method of concurrent electrical signal wiring optimization. The disclosed method and apparatus of concurrent electrical signal wiring optimization further provides an electronic package including alternating signals and reference planes. The disclosed method enables concurrent optimization by using a plurality of flexible package wiring solutions. These flexible package wiring solutions are discussed in the Detailed Description, infra. By using various combinations of the flexible package wiring solutions, increased design flexibility results when the method is employed in designing a single semiconductor electronic package. The signal wire structure derived from the disclosed method yields a vertical stacking of signal wires which can achieve low resistance. The disclosed method and resulting apparatus may be applied equally to integrated circuits or printed circuit boards.
In a first general aspect, the present invention provides a method for optimization of a signal wire structure, said method comprising: providing concurrent optimization of a plurality of wire parameters; providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters; providing an electronic package; determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions.
In a second general aspect, the present invention provides a substrate comprising: a first conductive plane; a dielectric layer positioned on said first conductive plane; a second conductive plane positioned on said dielectric layer, opposite said first conductive plane; a first conductive circuit member having a first surface positioned in said dielectric layer, said first surface substantially operatively positioned with respect to said first and second conductive planes; a second conductive circuit member having a second surface positioned in said dielectric layer, and spaced from said first conductive member, said second surface substantially operatively positioned with respect to said first and second conductive planes and with said first surface of said first conductive circuit member; and a plurality of conductive contacts electrically connecting said first surface of said first conductive circuit member and said second surface of said second conductive member.
In a third general aspect, the present invention provides a computer system comprising at least one semiconductor chip, wherein said semiconductor chip is connected to a plurality of wiring packages, and said wiring packages include at least one wiring package selected from the group consisting of: a superposed pair of signal wires, a side-by-side pair of signal wires having high characteristic impedance, a side-by-side pair of signal wires having low characteristic impedance, a staggered pair of signal wires, a single signal wire having a low resistance and a medium amount of electromagnetic coupling to other wires, a pair of low resistance signal wires, a single signal wire having a low resistance and a low amount of electromagnetic coupling to other wires, and a single signal wire having a high resistance.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of embodiments of the invention.
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patent: 5912809 (1999-06-01), Steigerwald et al.
patent: 6005895 (1999-12-01), Perino et al.
patent: 6084779 (2000-07-01), Fang
patent: 6127025 (2000-10-01), Bhatt et al.
patent: 6172305 (2001-01-01), Tanahashi
patent: 6218631 (2001-04-01), Hetzel et al.
patent: 6538524 (2003-03-01), Miller
Audet Jean
Budell Timothy W.
Buffet Patrick H.
Caron Alain
Elms Richard
Menz Douglas
Schmeiser Olsen & Watts
Steinberg William H.
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