Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-04-24
2004-08-10
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06775187
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a method of storing data using a flash memory device, such as a dual cell, charge trapping dielectric, electrically erasable and programmable memory device.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit (i.e., a binary data value have two states, such as a logical one and a logical zero) can be stored using a charge storing cell on a first “side” of the memory device and a second bit can be stored using a complimentary charge storing cell on a second “side” of the memory device.
Programming of such a memory device can be accomplished, for example, by hot electron injection. Hot electron injection involves “pulsing” the device by applying appropriate voltage potentials to each of a gate and a drain of the memory device for a specified duration. During the programming pulse, the source is typically grounded. Conventionally, the programming pulse voltage potentials are the same for the first programmed and the second programmed of the charge storing cells.
Reading of the memory device can be accomplished by applying an appropriate voltage to each of the gate and the drain and comparing the drain to source current (as an indication of device threshold voltage) against a reference value to determine if the read charge trapping cell is in a programmed or an unprogrammed state.
Even though conventional charge trapping dielectric flash memory devices are capable of storing charge corresponding to a programmed level in each of the charge storing cells, conventional programming techniques can lead to storing different amounts of charge in the respective charge storing cells and/or different charge profiles (i.e., placement or distribution of charge within the charge trapping layer) along a channel of the device in the respective charge storing cells. For example, programming one of the charge storing cells when the other charge storing cell is blank can result in a charge profile within the programmed charge storing cell that is relatively narrow. However, programming one of the charge storing cells when the other charge storing cell is charged can result in a charge profile within the programmed charge storing cell that is relatively wide.
As the width of the charge profile increases, the trapped electrons are spread over a larger lateral distance within the charge trapping layer. In addition, as the width of the charge profile increases, the more difficult it may become to mask, or cover-up, the charge during a read operation of the opposite charge storing cell by the application of a drain voltage during the read operation. In addition, as the width of the charge profile increases, the more difficult it may become to erase the charge trapping cell using, for example, a hot hole injection band-to-band (BTB) erase technique.
As a result, there is an ever increasing demand to improve the way with which charge is stored in memory devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a method of programming a charge trapping dielectric memory device having a first charge storing cell and a second charge storing cell. The method can includes pre-reading the first charge storing cell to determine if the first charge storing cell stores an amount of charge which increases a threshold voltage of the memory device over a specified threshold voltage; and programming the second charge storing cell to store an amount of charge corresponding to a charged program level by pulsing the memory device with a standard program pulse if the pre-reading indicates that the threshold voltage is less than the specified threshold voltage; otherwise programming the second charge storing cell to store an amount of charge corresponding to the charged program level by pulsing the memory device with a program pulse modified from the standard program pulse.
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Hamilton Darlene G.
Hsia Edward
Runnion Edward F.
Tanpairoj Kulachet
Advanced Micro Devices , Inc.
Phung Anh
Renner , Otto, Boisselle & Sklar, LLP
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