Semiconductor memory device having a trench capacitor

Details Semiconductor memory device having a trench capacitor Semiconductor memory device having a trench capacitor

2002-10-16

2004-04-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S068000, C257S071000, C257S296000, C257S298000, C257S905000, C257S906000, C438S242000, C438S243000, C438S386000

Reexamination Certificate

active

06727541

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-339277, filed Nov. 5, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates to a semiconductor memory device and a manufacturing method thereof, for example, a semiconductor memory device and its manufacturing method enhancing integrality of memory elements including a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
Conventionally, a transistor and a capacitor comprising a semiconductor memory device are formed as follows.
A top view of a manufacturing step of the semiconductor memory device is shown in FIG.
15
(
a
). A cross sectional view corresponding to a broken line in
FIG. 15
(
a
) is shown in FIG.
15
(
b
). As shown in FIGS.
15
(
a
) and
15
(
b
), an oxide layer
102
is deposited on a P-type semiconductor substrate
101
and then a resist layer
103
is formed on the oxide layer
102
. By using a lithography technique which is known, the resist layer
103
is patterned and then by using a RIE method (Reactive Ion Etching method), the oxide layer
102
is patterned, and a trench pattern is formed in the oxide layer
102
.
As shown in
FIG. 16
, by using an anisotropic etching method, a trench is formed in the P-type semiconductor substrate
101
and then an As doped oxide layer
104
is formed on the resultant. After that, by using a etch back method, the As doped oxide layer
104
is removed up to a position 1 &mgr;m in depth from an upper surface of the surface of the P-type semiconductor substrate
101
. By thermally diffusing arsenic (As) in the As doped oxide layer
104
to the P-type semiconductor substrate
101
, a capacitor electrode diffusion layer
105
which is served as a plate electrode of DRAM is formed.
By using a treatment in fluoric atmosphere, the As doped oxide layer
104
is removed selectively and then, as shown in
FIG. 17
, an oxide layer
106
which is served as a capacitor insulation layer is formed on a side wall of the trench. An As doped poly crystalline
107
is deposited on the oxide layer
106
in the trench and then, by using a etch back method, the As doped poly crystalline
107
is removed up to a position 1 &mgr;m in depth from an upper surface of the surface of the P-type semiconductor substrate
101
. Furthermore, an oxide layer
108
is formed on a surface of the oxide layer
106
and on the As doped poly crystalline silicon layer
107
in the trench. After that, by using a etch back method, the oxide layer
106
and
108
are removed up to a position 300 nm in depth from an upper surface of the surface of the P-type semiconductor substrate
101
. And then, An As doped poly crystalline silicon layer
109
is deposited on the oxide layer
108
and a surface of the trench and then, by using a etch back method, the As doped poly crystalline silicon layer
109
is removed up to 50 nm in depth from an upper surface of the P-type semiconductor substrate
101
. By thermally diffusing method, arsenic (As) in the As doped poly crystalline silicon layer
109
are diffused to the P-type semiconductor substrate
101
, thereby forming a N type diffusion layer
110
which is served as a source or a drain region of a memory cell transistor. As mentioned above, the memory cell with a trench capacitor is formed.
A top view of the manufacturing step of the semiconductor memory cell is shown in FIG.
18
(
a
) and a cross sectional view corresponding to a broken line in FIG.
18
(
a
) is shown in FIG.
18
(
b
). As shown in
FIG. 18
(
a
) and (
b
), a resist layer
111
is formed on a resultant and then patterned. After that, by using a RIE method, portions of the oxide layer
102
, the trench and the P-type semiconductor substrate
101
are removed and furthermore, the resist layer
111
is removed by ashing method.
As shown in
FIG. 19
, after an oxide layer
112
is deposited on the P-type semiconductor substrate
101
and the As doped poly crystalline silicon layer
109
. And then, by using CMP method (Chemical Mechanical Polishing method), the oxide layer
112
is polished up to a surface of the P-type semiconductor substrate
101
, thereby forming a element isolation insulation layer comprising the oxide layer
112
.
A top view of the manufacturing step of the semiconductor memory cell is shown in FIG.
20
(
a
) and a cross sectional view corresponding to a broken line in FIG.
20
(
a
) is shown in FIG.
20
(
b
). As shown in FIGS.
20
(
a
) and (
b
), a oxide layer
113
which is served as a gate insulating film is formed on an upper surface of the P-type semiconductor substrate
101
. An As doped poly crystalline silicon layer
114
, a WSi layer
115
and a SiN layer
116
are formed in order, and then a resist layer
117
is formed on the SiN layer
116
. The resist layer
117
is patterned to a word line pattern. After that, by using the patterned resist layer
117
as a mask and using a RIE method, the SiN layer
116
, the WSi layer
115
and the As doped poly crystalline silicon layer
114
are etched in order, thereby forming a word line comprising the As doped poly crystalline silicon layer
114
and the WSi layer
115
which are used as a gate electrode.
The patterned resist layer
117
which is used as a word line pattern, is removed by an ashing method. A top view of a situation where the patterned resist layer
117
was removed is shown in FIG.
21
(
a
) and a cross sectional view corresponding to a broken line in FIG.
21
(
a
) is shown in FIG.
21
(
b
). As shown in FIGS.
21
(
a
) and (
b
), a SiN layer
118
is deposited on the resultant. And then, by using a RIE method, a portion of the SiN layer
118
is removed, thereby remaining a side wall insulation film which is consistent of the SiN layer
118
on side surfaces of the As doped poly crystalline silicon layer
114
, the WSi layer
115
and the SiN layer
116
. After that, Ions of Arsenic (As) are implanted to an exposed surface of the P-type semiconductor substrate
101
, thereby forming N type diffusion layers
119
which are used as a source or a drain electrode. And then, a BPSG layer
120
is deposited on the resultant and then a reflow step is performed, thereby flattening an upper surface of the BPSG layer
120
. A resist layer
121
is formed on the BPSG layer
120
, and then the resist layer
121
is patterned to a contact pattern by using a lithography method. After that, by using the patterned resist layer
120
as a mask and using a RIE method, the BPSG layer
120
and the oxide layer
113
which are exposed are removed, thereby forming a contact hole on the N type diffusion layer
119
served as a source or a drain region.
The patterned resist layer
121
which was used as mask, is removed by an ashing method. A top view of a situation where the patterned resist layer
121
was removed is shown in FIG.
22
(
a
) and a cross sectional view corresponding to a broken line in FIG.
22
(
a
) is shown in FIG.
22
(
b
). As shown in FIGS.
22
(
a
) and (
b
), an As doped poly crystalline silicon layer
122
is deposited on the resultant. And then, by using an etch back method, a portion of the As doped poly crystalline silicon layer
122
is removed up to a position 300 nm in depth from an upper surface of the BPSG layer
120
, thereby remaining a portion of the As doped poly crystalline silicon layer
122
in the contact hole. And then, a resist layer
123
is formed on the resultant and patterned to a bit line pattern. After that, by using a RIE method, a portion of the BPSG layer
120
is removed up to a position 300 nm in depth from an upper surface of the BPSG layer
120
, thereby forming grooves which are served as a bit line pattern.
The patterned resist layer
123
which is used as a bit line pattern, is removed by an ashing method. A top view of a situation where the patterned resist layer
123
was removed is shown in FIG.
23
(
a
) and a cross sectional view corresponding

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