Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-10-31
2004-09-07
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230060, C365S233100
Reexamination Certificate
active
06788606
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention refers to memory cells in a memory element and particularly to a refresh of memory cells in a memory element.
2. Description of the Related Art
In battery-operated devices, dynamic random access memories (DRAM), wherein stored data are often kept in the DRAM, when the device is turned off, are used more and more often. This takes place in the so-called selfrefresh mode. Thereby, a timer is running in the DRAM chip, which regularly supplies impulses by which successively all word lines are activated and all memory cells of each word line are refreshed.
A memory array consists, e.g., of 512 word lines, each of which controls 4096 memory cells. So, for refresh, each memory line and each group of memory cells belonging to a word line, respectively, is read out every 64 ms and the read content is written back into the cells, whereby the memory content is maintained. The cycle time of this operation—in this example 64 ms—is also called retention time. Since about 75% of the energy need in the selfrefresh mode is needed for charging the cells in rewriting, it is generally attempted to increase the cycle time of the refresh.
SUMMARY OF THE INVETION
It is the object of the present invention to provide an improved concept for refreshing memory cells.
The present invention is a method for refreshing a plurality of memory cells in a memory element, wherein a first number of memory cells has a first retention time for holding a content of the memory cell, and wherein a second number of memory cells has a second retention time for holding the content of the memory cell, having:
refreshing the first number of memory cells when reaching the first retention time; and
refreshing the second number of memory cells when reaching the second retention time.
The present invention is an apparatus for refreshing a plurality of memory cells in a memory element, wherein a first number of memory cells has a first retention time for holding a content of each of the first number of memory cells, and wherein a second number of memory cells has a second retention time for holding a content of each of the second number of memory cells. The apparatus is provided for refreshing the first number of memory cells when reaching the first retention time, and for refreshing the second number of memory cells when reaching the second retention time.
Preferred developments are defined in the subclaims.
The present invention makes use of the fact that, due to manufacturing reasons, in a typical memory element only individual memory cells have a short retention time during which their data content is maintained readably, most memory cells, however, can hold their data content much longer (up to 1 s) easily. With reference to the above-mentioned numerical example, therefore only individual memory cells actually have to be refreshed every 64 ms. According to the present invention, a refresh is offered every 64 ms, most memory cells, however, only experience a refresh after a multiple of this time, such as every 256 ms. Only word lines and memory cells in word lines, respectively, containing bad memory cells are refreshed with a cycle time of 64 ms.
Since the bad memory cells and the memory cells with a short retention time, respectively, are disposed at a different position in each memory element chip, it has to be possible to adjust and store, respectively, individually, which word lines and memory cells of which word lines, respectively, should experience a fast and frequent, respectively, refresh. Therefore, laser fuses and fusing means, respectively, are used, which can be fuse-blown via a laser beam to break an electrical connection. Via a respective number of laser fuses one word line address can be adjusted, respectively. A comparator compares in each refresh signal the applied address with the one or the ones programmed with the laser fuses. If the applied and one of the programmed word line addresses match, a refresh for the memory cells of the respective word line is arranged. Additionally, it can be determined with an enable bit, whether a word line should be operated with a short refresh cycle time at all.
Preferably, only the address of the address bus will be illustrated with laser fuses and not each individual word line. For example, each address of a total of 512 word lines, can be illustrated by nine laser fuses. Therefore, the use of an enable laser fuse is practical. If the addresses of several word lines are to be storable, to set same to a short retention time, a respective multiple number of laser fuses or the entire circuit have to be present and built in correspondingly often, respectively.
According to the present invention, it is achieved that electrical power for the refresh of memory cells, which do not yet have to be refreshed, is saved. The total power requirement of the memory element in the refresh mode is therefore reduced significantly.
REFERENCES:
patent: 5629898 (1997-05-01), Idei et al.
patent: 6529433 (2003-03-01), Choi
patent: 0 790 620 (1997-08-01), None
Satoru Takase et al.: “A 1.6-Gbyte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme”,IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999, pp. 1600-1606.
Youji idei et al.: “Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Register”,IEEE Journal of Solid-State Circuits, vol. 33, No. 2, Feb. 1998, pp. 253-259.
Yasuo Miyamoto et al.: “Study of new refresh method for low data retention current”, 1993, p. 5-268.
Fibranz Heiko
Fischer Helmut
Auduong Gene N.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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