Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-01
2004-09-14
Thomas, Tom (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S372000
Reexamination Certificate
active
06791147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having twin wells and a manufacturing method thereof.
2. Description of Related Art
There are a variety of different types of SRAMs, one form of semiconductor memory devices. One type of SRAMs employs CMOS devices. Among CMOS devices, twin-well type devices are mainstream devices. A twin-well type device has a p-well and an n-well that are formed in a semiconductor substrate. For example, Japanese Unexamined Patent Publication No. 8-330528 describes an SRAM employing twin wells.
FIG. 18
is a cross-sectional view showing a memory cell-area and a peripheral circuit area of the SRAM described in the publication.
The construction of the memory cell area is discussed first. A semi-recessed LOCOS oxidation layer
204
is formed on the main surface of a silicon substrate
200
. A p-well
202
is formed over the entire surface of the main surface of the silicon substrate
200
. The p-well
202
extends to a level deeper than the semi-recessed LOCOS oxidation layer
204
.
An n-well
206
is formed in a predetermined area of the p-well
202
. The n-well
206
is formed at a level shallower than the semi-recessed LOCOS oxidation layer
204
. A p-channel transistor
208
having a pair of p-type source/drains
210
is formed in the n-well
206
.
An n-channel transistor
214
having a pair of n-type source/drains
212
is formed in a predetermined area of the p-well
202
. The n-channel transistor
214
is isolated from the p-channel transistor
208
by the semi-recessed LOCOS oxidation layer
204
.
The construction of the peripheral circuit area is now discussed. A semi-recessed LOCOS oxidation layer
216
is formed on the main surface of the silicon substrate
200
. A p-well
218
and an n-well
220
are formed on the main surface of the silicon substrate
200
. The border between the p-well
218
and the n-well
220
is present beneath the semi-recessed LOCOS oxidation layer
216
. The depths of the p-well
218
and the n-well
220
are generally equal to the depth of the p-well
202
.
A p-channel transistor
224
having a pair of p-type source/drains
222
is formed in the n-well
220
. A n-channel transistor
228
having a pair of n-type source/drains
226
is formed in the p-well
218
.
To miniaturize memory cells, the length of the device isolation structure (such as a semi-recessed LOCOS oxidation layer) of the memory cell area needs to be shortened. To prevent the generation of a substrate current that causes latchup, the spacing between one well and the source/drain of another well formed adjacent to the one well needs to be longer than a certain distance.
In the technique discussed in the above publication, the n-well
206
is formed at a level shallower than the semi-recessed LOCOS oxidation layer
204
. This arrangement prevents the distance between the n-well
206
and the n-type source/drain
212
from becoming too short while providing the semi-recessed LOCOS oxidation layer
204
with an adequate length.
In the technique disclosed in the publication described above, however, the depth of the p-well
202
is different from the depth of the n-well
206
. This arrangement creates a difference in performance between the n-channel transistor
214
and the p-channel transistor
208
. This leads to an imbalance between the n-channel transistor
214
and the p-channel transistor
208
, degrading a state-sustaining function of each flip-flop in the SRAM.
Furthermore, the p-type source/drain
210
is formed in the n-well
206
, and the n-well
206
is formed at a level shallower than the semi-recessed LOCOS oxidation layer
204
. Accordingly, this arrangement leads to a problem as to how a well contact region that connects to a wiring for fixing the potential of the n-well
206
is formed. Forming the well contract region in each cell is contemplated. However, such a construction increases the cell size.
A shallow n-well
206
requires that the p-type source/drain
210
be formed at a considerably shallower level. The drain current of the p-channel transistor
208
is substantially smaller than the drain current of the n-channel transistor
214
. When an operating voltage is high, this is not a problem. However, the operating voltage is lowered as the SRAM is miniaturized. For example, when the p-channel transistor
208
is operated from 2 V, there is fear that a small current causes the p-channel transistor
208
to be unable to achieve its required performance.
SUMMARY OF THE INVENTION
The present invention has been developed to solve the above-described problems. It is an object of the present invention to provide a semiconductor memory device and a manufacturing method thereof, which prevents the distance between one well and the source/drain of another well form-ed adjacent to the one well from becoming too short without increasing the length of the device isolation structure.
In accordance with one embodiment of the present invention, a semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device may include a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. In one feature of the embodiment, the second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is generally equal in depth to the second well, wherein the second and third wells are formed down to a level lower than the device isolation structure.
In accordance with one embodiment of the present invention, the well in the peripheral circuit area and the wells in the memory cell area may be different in depth. In a preferred embodiment, the depths of the second and third wells formed in the memory cell area are shallower than that of the first well formed in the peripheral circuit area.
In accordance with one embodiment of the present invention, the second well and the third well beneath the device isolation structure may overlap with one another, and an overlapped area between the second well and the third well beneath the device isolation structure is reduced. The reason for this will be described in the discussion of the embodiments.
In one feature of an embodiment of the present invention, the distance between one well and the source/drain of another well formed adjacent to the one well is prevented from becoming too short without increasing the length of the device isolation structure.
Examples of the device isolation structure in the present invention include a LOCOS oxidation layer, a semi-recessed LOCOS oxidation layer, a shallow trench (as deep as 0.4 to 0.8 &mgr;m), and the like. The term “source/drain” refers to at least one of source and drain.
In accordance with one embodiment of the present invention, the second well and the third well may be equal in depth. This arrangement precludes an imbalance in performance between transistors attributable to a well depth difference in the memory cell area. It is noted that, in this specification, the term “equal depth” is not strictly limited to the same depth but also covers a well depth difference that causes substantially no imbalance in performance between transistors.
Since the second well and the third well may be equal in depth in accordance with embodiments of the present invention, the depth of the source/drain of the second well and the depth of the source/drain of the third well can be equalized to one another. This arrangement causes substantially no imbalance in performance between transistors, attributable to a depth difference between the sources/drains in the memory cell area.
In accordance with one embodiment of the present invention, the sources/drains formed in the secon
Karasawa Junichi
Kumagai Takeshi
Watanabe Kunio
Lee Eugene
Seiko Epson Corporation
Thomas Tom
LandOfFree
Semiconductor memory device and method for manufacturing the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and method for manufacturing the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method for manufacturing the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3272101