Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-06
2004-08-31
Lebentriti, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S660000, C438S667000, C438S928000
Reexamination Certificate
active
06784099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention relates to a dual-sided semiconductor device and a method for forming the device and, more particularly, to a dual-sided semiconductor device and a method for forming the device with a resistive element that requires very little silicon surface area.
2. Description of the Related Art.
A dual-sided semiconductor device is a device that has electrical circuits on both sides of a wafer. Thus, unlike more conventional semiconductor devices that utilize only one side of a wafer, a dual-sided device utilizes both sides of the wafer. As a result, packaged dual-sided semiconductor devices consume significantly less circuit-board real estate than conventional single-sided devices.
FIG. 1
shows a cross-sectional drawing that illustrates a dual-sided semiconductor device
100
. As shown in
FIG. 1
, device
100
includes a wafer
110
that has a top side
112
and a bottom side
114
. As further shown in
FIG. 1
, device
100
also has electrical circuits
120
which are formed on top side
112
, and electrical circuits
122
which are formed on bottom side
114
. Electrical circuits
120
and
122
typically communicate with the outside world via wires that are connected to pads that form a part of circuits
120
and
122
.
Thus, as shown in
FIG. 1
, circuits
120
and
122
both share the central portion of wafer
110
. As a result, whatever voltage is present on the central portion of wafer
110
can effect the operation of both circuits
120
and
122
. To reduce the likelihood of undesirable effects, the voltage on the central portion of wafer
110
Is usually held at a fixed value.
One problem with semiconductor devices is that It is difficult to form large resistive elements on a wafer without consuming large amounts of silicon surface area. The space requirements of large resistive elements are often so severe that external devices must be used. Thus, there is a need for a method of forming large resistive elements on a wafer that consume much less silicon surface area.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a large resistive element on a dual-sided semiconductor device that substantially reduces the amount of silicon surface area required by the resistive element. As a result, the present invention allows large resistive elements to be integrated into semiconductor circuits.
The method of the present invention forms a dual-sided semiconductor device from a wafer that has a top surface, a bottom surface, and a dopant concentration. The method includes the step of forming a layer of masking material on the top surface of the wafer. The method also includes the step of patterning the layer of masking material to form a first opening in the layer of masking material that exposes a first region on the top surface.
The method further includes the step of forming a first opening in the top side of the wafer, and a doped region in the wafer between the first opening in the wafer and the bottom surface of the wafer after the layer of masking material has been patterned. The doped region has a top surface exposed by the first opening in the wafer, and a dopant concentration greater than the dopant concentration of the wafer.
The method additionally includes the step of forming a layer of conductive material to fill up the first opening in the wafer. The method also includes the step of planarizing the layer of conductive material to form a first conductive region formed over the doped region.
The present invention also includes a dual-sided semiconductor device that is formed on a wafer that has a top surface, a bottom surface, and a dopant concentration. The device includes a doped region that is formed in the wafer. The doped region, in turn, has a top surface, a bottom surface, and a dopant concentration that is greater than the dopant concentration of the wafer.
The device also includes an upper region of conductive material that is formed in the wafer over the top surface of the doped region. The upper region of conductive material has a top surface that is substantially planar with the top surface of the wafer.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
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Lebentriti Michael S.
National Semiconductor Corporation
Pickering Mark C.
Wilson Christian D.
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