Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2004-01-13
2004-10-12
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S686000, C257S734000, C257S738000, C174S255000, C174S256000
Reexamination Certificate
active
06803658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring substrate having top-flattened solder bumps projecting from the main surface thereof, and to a method for manufacturing the same.
2. Description of the Related Art
A known wiring substrate includes a resin dielectric layer and a conductor layer formed in a predetermined pattern on the resin dielectric layer. An example of such a wiring substrate is shown in
FIG. 5
, which is an enlarged partially broken away, sectional view of a substrate
101
and which shows a portion located on the side toward the main surface. The substrate
101
has a core substrate (resin dielectric layer)
103
at its center. One or more resin dielectric layers
105
are formed in layers on either side of the core substrate
103
, and a solder resist layer (resin dielectric layer)
107
is formed on the dielectric layer
105
on one side of the core substrate
103
, thereby providing the main surface of the substrate
101
.
A plurality of substantially cylindrical through-hole conductors
111
are formed in the core substrate
103
at predetermined positions and are filled with respective resin fillers
112
. A plurality of through-holes
113
which enable the formation of vias are formed in the resin dielectric layer
105
at predetermined positions, and via conductors
115
are formed in the corresponding through-holes
113
. A plurality of openings
117
which provide exposure of respective pads
116
are formed in the solder resist layer
107
at predetermined positions. Further, a first conductor layer
118
including wiring lines and pads is formed in a predetermined pattern between the core substrate
103
and the resin dielectric layer
105
and is connected to the through-hole conductors
111
formed in the core substrate
103
and the via conductors
115
formed in the resin dielectric layer
105
. In addition, a second conductor layer
119
including wiring lines and pads is formed in a predetermined pattern between the resin dielectric layer
105
and the solder resist layer
107
and is connected to the via conductors
115
. When a plurality of the resin dielectric layers
105
are formed, a conductor layer (not shown) is provided between the resin dielectric layers corresponding to layer
105
.
In the substrate
101
, bumps are formed of, for example, solder or gold on the corresponding pads
116
formed in the solder resist layer
107
, so as to serve as terminals for electrical connection. Further, in order to ensure connection to an electronic component (e.g., an IC chip, a chip capacitor, a chip resistor, or the like) to be mounted on the substrate
101
, the bumps are flattened at their tops by use of a flat pressing surface, thereby forming top-flattened solder bumps corresponding to bump
120
.
Because the substrate
101
uses a resin layer of substantially uniform thickness as the resin dielectric layer
105
, portions of the resin dielectric layer
105
located above the first conductor layer
118
present between the core substrate
103
and the resin dielectric layer
105
rise slightly. In the course of forming the resin dielectric layer
105
, the resin dielectric layer
105
is pressed while being heated, and thus the surface of the resin dielectric layer
105
is flattened to a certain extent. However, for example, as shown in
FIG. 6
, a portion of the resin dielectric layer
105
which is formed on a solid layer
121
(which is a portion of the first conductor layer
118
and extends over a certain area) unavoidably rises to a certain extent in relation to the remaining portion of the resin dielectric layer
105
. As a result, a first pad
116
B, which is located within a region which is formed by projecting the solid layer
121
toward the main surface (hereinafter simply referred to as a “region above the solid layer”) is formed at a raised position whereas a second pad
116
C is located outside the region above the solid layer. Thus, as represented by dotted lines in
FIG. 6
, the solder bump
122
B formed on the first pad
116
B and the solder bump
122
C formed on the second pad
116
C are of the same size, but differ slightly in the position of the vertex, i.e., bump
122
B projects outwardly from substrate
101
slightly more than bump
122
C. These solder bumps
122
B and
122
C are flattened at their tops through pressing, through the use of a common, flat pressing surface
123
, and are thus formed into a first top-flattened solder bump
120
B and a second top-flattened solder bump
120
C, respectively. Since the difference in the positions of the vertices of the bumps
122
B and
122
C results in a difference in the amount of solder to be crushed in the course of the flattening process, the diameter M
1
of the top face of the top-flattened solder bump
120
B is greater than the diameter M
2
of the top face of the top-flattened solder bump
120
C, as shown in FIG.
6
. Actual measurements have revealed that a difference of 2 to 3 &mgr;m in positional height between the pads
116
leads to a difference of about 10 &mgr;m in top face diameter between the top-flattened solder bumps
120
.
It will be appreciated that the connection terminals of an electronic component to be mounted on the substrate
101
are formed in a very uniform fashion, and that the fact that the top-flattened solder bumps
120
of the substrate
101
differ in top face diameter can, in some cases, result in variations in connection accuracy among the connections when the electronic component is mounted on the substrate
101
.
SUMMARY OF THE INVENTION
An object of the invention is to provide an improved wiring substrate in which top-flattened solder bumps have substantially the same top face diameter irrespective of the presence of a solid layer, and to thereby improve the accuracy of the connections between the wiring substrate and an electronic component mounted thereon.
Another object of the present invention is to provide a method for manufacturing the improved wiring substrate.
According to one aspect of the invention, in order to achieve the above objects, the present invention provides a method for manufacturing a wiring substrate having a main surface, a back surface, and a plurality of top-flattened solder bumps projecting from the main surface. The method comprises the steps of: forming a solid layer on a core substrate so as to partially cover the core substrate; forming at least one resin dielectric layer on the solid layer and the core substrate; forming a plurality of pads on the resin dielectric layer in such a manner that the plurality of pads are exposed at the main surface of the wiring substrate, the pads including first pads located within a region above the solid layer and second pads located outside of the region; applying, through printing, solder paste onto the plurality of pads such that the amount of solder paste applied onto each of the first pads is smaller than that applied onto each of the second pads; melting the applied solder paste, through reflowing, so as to form substantially hemispherical solder bumps; and flattening top portions of the substantially hemispherical solder bumps through pressing of a flat pressing surface against the top portions, thereby forming the top-flattened solder bumps.
According to an important feature of the present invention, solder paste is applied through printing onto a plurality of pads which are exposed at the main surface so that the solder paste can be applied thereto. Next, the applied solder paste is melted to obtain the substantially hemispherical solder bumps. Subsequently, the aforementioned flat pressing surface is pressed against top portions of the solder bumps so as to obtain the top-flattened solder bumps. Relative to the solder paste application step, each pad is classified as first pad or second pad in accordance with whether or not the pad is located within the region above the solid layer and, as indicated above, a pad is classified as first pad when the pad is located within the region above the solid layer, and a
Hunt, Jr. Ross F.
Nelms David
NGK Spark Plug Co. Ltd.
Stites & Harbison PLLC
Tran Long
LandOfFree
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