Non-volatile semiconductor memory device of which bit line...

Details Non-volatile semiconductor memory device of which bit line... Non-volatile semiconductor memory device of which bit line...

2002-08-05

2004-04-06

Mai, Son (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S326000, C438S257000, C438S424000

Reexamination Certificate

active

06717207

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device wherein storage of binary values is possible.
2. Description of the Background Art
An NROM (nitride read-only memory) type flash EEPROM (hereinafter referred to as NROM), which is a type of flash EEPROM, has been gaining attention as a type of non-volatile semiconductor memory device. An NROM has been reported in U.S. Pat. No. 6,011,725 and U.S. Pat. No. 5,768,192.
FIG. 18
is a layout view showing a portion of a memory cell array of an NROM according to a prior art.
In reference to
FIG. 18
, the memory cell array of the NROM includes a plurality of word lines
1
arranged in rows and a plurality of bit lines
2
arranged in columns. Each memory cell MC is arranged in a region
3
surrounded by dotted lines.
FIG. 19
is a schematic cross sectional view along line segment XIX—XIX in FIG.
18
.
In reference to
FIG. 19
, bit lines
2
are formed at predetermined intervals on the main surface of a p well
10
. A bit line
2
is a diffusion bit line formed as an n-type diffusion region. A silicon oxide film
11
is formed on each bit line
2
. A silicon oxide film
12
is formed on the main surface of p well
10
between two bit lines
2
. A nitride film
13
for storing a charge is formed on silicon oxide film
12
. A silicon oxide film
14
is formed on nitride film
13
. A word line
1
is formed above silicon oxide films
14
and
11
. Word line
1
is formed of polysilicon.
As shown in
FIG. 19
, a charge storage portion of a memory cell of the NROM has a layered structure (hereinafter referred to as an ONO layered structure) of silicon oxide film
12
, nitride film
13
and silicon oxide film
14
. In the NROM a charge of one bit is stored in a region, positioned above each bit line
2
, at each of the two ends of nitride film
13
in the ONO layered structure. According to the above-described structure, two bits can be stored in one memory cell of the NROM. In addition, as shown in
FIG. 18
, memory cells next to each other with a bit line between them share bit line
2
placed between the neighboring memory cells as a source or a drain.
As a result, the area occupied for one bit is greatly reduced to 2.5 F
2
in the NROM in comparison with 5 F
2
to 15 F
2
in a conventional NOR-type flash EEPROM.
As described above, an enhancement of integration is possible in the NROM and cost can be reduced.
As shown in
FIG. 19
, however, element isolation regions do not exist between the bit lines of the NROM unlike in the conventional flash EEPROM. Accordingly, the withstand voltage between bit lines deteriorates leading to the possibility of the occurrence of charge leakage.
In addition, as shown in
FIG. 19
, bit line
2
of the NROM is formed through diffusion. Accordingly, the electrical resistance of the bit line is high. As a result, there is a possibility that the performance of the NROM may be inferior to that of the conventional flash EEPROM.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a non-volatile semiconductor memory device wherein the occurrence of current leakage is prevented by increasing the withstand voltage between bit lines so that an increase in performance can be implemented and of which the cost of manufacture is inexpensive.
A non-volatile semiconductor memory device according to the present invention includes a semiconductor substrate of a first conductive type having a main surface, a plurality of conductive regions of a second conductive type, a plurality of insulating regions, a first insulating film, a charge storage film, a second insulating film and a plurality of conductive lines. The plurality of conductive regions is formed in the main surface of the semiconductor substrate. The plurality of insulating regions is formed in the main surface of the semiconductor substrate and is arranged so as to alternate with the plurality of conductive regions. The first insulating film is formed on the main surface of the semiconductor substrate. The charge storage film is formed on the first insulating film and has a plurality of storage regions. The second insulating film is formed on the charge storage film. The plurality of conductive lines is formed on the second insulating film.
According to the present invention, an isolation oxide film is formed between each pair of bit lines in the layout of the memory cell array of the non-volatile semiconductor memory device. Accordingly, the withstand voltage between bit lines is increased so that charge leakage can be restricted.
Furthermore, bit lines are formed of a metal instead of being diffusion bit lines and, therefore, the resistance of the bit lines can be reduced. As a result, the performance of the non-volatile semiconductor memory device can be increased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5679591 (1997-10-01), Lin et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5851879 (1998-12-01), Lin et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6081456 (2000-06-01), Dadashev
patent: 6174758 (2001-01-01), Nachumovsky
patent: 6512263 (2003-01-01), Yuan et al.
patent: 2002/0187615 (2002-12-01), Liou
patent: 63-108778 (1988-05-01), None
patent: 5-326976 (1993-12-01), None
Eitan, et al, “Can NROM, A 2-Bit, Trapping Storage NVM Cell, Give A Real Challenge to Floating Gate Cells?” International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 1-3.

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