Single anneal for dopant activation and silicide formation

Details Single anneal for dopant activation and silicide formation Single anneal for dopant activation and silicide formation

2000-11-15

2004-08-17

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S308000, C438S664000

Reexamination Certificate

active

06777275

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved salicide process of forming metal silicide contacts.
BACKGROUND OF THE INVENTION
An important aim of ongoing research in the semiconductor industry is the reduction in the dimensions of the devices used in integrated circuits. Planar transistors, such as metal oxide semiconductor (MOS) transistors, are particularly suited for use in high-density integrated circuits. As the size of the MOS transistors and other active devices decreases, the dimension the size of the source/drain regions and gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such a diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, for example on the order of 1,000 Å or less thick are generally required for acceptable performance in short channel devices.
Metal silicide contacts are typically used to provide low resistance contacts to source/drain regions and gate electrodes. The metal silicide contacts are conventionally formed by depositing a conductive metal, such as titanium, cobalt, tungsten, or nickel, on the source/drain regions and gate electrodes by physical vapor deposition (PVD), e.g. sputtering or evaporation; or by a chemical vapor deposition (CVD) technique. Subsequently, heating is performed to react the metal with underlying silicon to form a metal silcide layer on the source/drain regions and gate electrodes. The metal silicide has a substantially lower sheet resistance than the silicon to which it is bonded. Selective etching is then conducted to remove unreacted metal from the non-silicided areas, such as the dielectric sidewall spacers. Thus, the silicide regions are aligned only on the electrically conductive areas. This self-aligned silicide process is generally referred to as the “salicide” process.
A portion of a typical semiconductor device
40
is schematically illustrated in FIG.
1
A and comprises a silicon-containing substrate
10
with source/drain regions
34
formed therein. Gate oxide layer
14
and gate electrode
16
are formed on the silicon-containing substrate
10
. Sidewall spacers
30
are formed on opposing side surfaces
18
of gate electrode
16
. Sidewall spacers
30
typically comprise silicon based insulators, such as silicon nitride, silicon oxide, or silicon carbide. The sidewall spacers
30
mask the side surfaces
18
of the gate
16
when metal layer
36
is deposited, thereby preventing silicide from forming on the gate electrode side surfaces
18
.
After metal layer
36
is deposited, heating is conducted at a temperature sufficient to react the metal with underlying silicon in the gate electrode
16
and substrate surface
12
to form conductive metal silcide contacts
38
(FIG.
1
B). After the metal silcide contacts
38
are formed, the unreacted metal
36
is removed by etching, as with a wet etchant, e.g., an aqueous H
2
O
2
/NH
4
OH solution. The sidewall spacer
30
, therefore, functions as an electrical insulator separating the silicide contact
38
on the gate electrode
16
from the metal silicide contacts
38
on the source/drain regions
34
, as shown in FIG.
1
B.
Various metals react with Si to form a silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create silcides (TiSi
2
, CoSi
2
) when manufacturing semiconductor devices utilizing salicide technology.
Use of a TiSi
2
layer imposes limitations on the manufacture of semiconductor devices. A significant limitation is that the sheet resistance for lines narrower than 0.35 micrometers is high, i.e., as TiSi
2
is formed in a narrower and narrower line, the resistance increases. Another significant limitation is that TiSi
2
initially forms a high resistivity phase (C
49
), and transformation from C
49
to a low resistivity phase (C
54
) is nucleation limited, i.e., a high temperature is required to effect the phase change.
Cobalt silicide, unlike TiSi
2
, exhibits less linewidth dependence of sheet resistance. However, CoSi
2
consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with silicon on insulator (SOI) substrates. Without enough Si to react with Co to form CoSi
2
, a thin layer of CoSi
2
results. The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material; thus a thicker silicide layer increases semiconductor device speed, while a thin silicide layer reduces device speed.
Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi
2
and CoSi
2
because many limitations associated with TiSi
2
and CoSi
2
are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni and Co through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi
2
and CoSi
2
are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silcide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi
2
and CoSi
2
. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
In addition to the annealing step to form the silicide, there are additional high temperature heating steps in conventional MOS semiconductor device fabrication processes. Conventional processes also require one or more high temperature annealing steps to activate the source/drain regions and source/drain extensions. For example, in addition to the anneal at greater than 1,000° C. to activate the source/drain dopants, the formation of devices with CoSi
2
contacts requires a two-step annealing process which includes a first annealing at approximately 500° C. and a second annealing at approximately 800° C. Multiple high temperature heat treatment steps increase the manufacturing costs and the complexity of semiconductor device fabrication. High temperature annealing increases lateral and vertical diffusion of the dopants in the source/drain regions. Increased vertical diffusion of dopant results in slower, deeper junctions, while increased lateral diffusion of the dopant can result in junction leakage. Furthermore, every time a wafer is heated and cooled crystal damage from dislocations occur. A high concentration of dislocations can cause device failure from leakage currents.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
SUMMARY OF THE INVENTION
There exists a need in the semiconductor device manufacturing art to provide a process for forming metal silicide contacts for planar transistors with fewer high temperature annealing steps. There exists a need in this art to implant dopant in the source/drain regions without requiring a high temperature anneal to activate the dopants. There exists a need in this art to provide doped source/drain regions with met

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