Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2003-03-04
2004-10-19
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000, C327S333000
Reexamination Certificate
active
06806734
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shifting circuit and to an active matrix driver including such a circuit.
2. Description of the Related Art
Level shifting circuits are required, for example, in digital metal oxide semiconductor (MOS) circuits which are required to respond to input signals of substantially lower amplitude than the supply voltage. Such circuits are used in silicon-on-insulator (SOI) circuits which are required to interface with low voltage signals, for example having amplitudes typically in the region of from 1 to 5 volts, but which typically operate at substantially higher supply voltages, for example in the region of between 10 and 20 volts. A specific example of such an arrangement is a monolithic driver circuit for a flat panel active matrix display fabricated with poly-silicon thin-film transistors (TFTs). Another application of level shifting circuits is in interfaces between different logic families, for example TTL and CMOS.
FIG. 1
of the accompanying drawings illustrates a known type of level shifting circuit comprising n-channel transistors
1
and
2
whose sources are connected to ground and whose drains are connected to the drains of p-channel transistors
3
and
4
, respectively. The sources of the transistors
3
and
4
are connected to the drains of p-channel transistors
5
and
6
, respectively, whose sources are connected to a power supply line vdd. The drains of the transistors
1
and
3
are connected to the gate of the transistor
6
and to a complementary output !OUT whereas the drains of the transistors
2
and
4
are connected to the gate of the transistor
5
and to an output OUT. The gates of the transistors
1
and
3
are connected to an input IN whereas the gates of the transistors
2
and
4
are connected to a complementary input !IN.
Although such an arrangement is capable of providing level shifting of a digital input signal such that the output voltage swing is greater than the input voltage swing, this arrangement is not tolerant of transistors with threshold voltages which are of a similar level to the input signal. For example, poly-silicon transistors may have a threshold in the region of 3 volts and so such a circuit can only operate with input signals having a higher level substantially greater than this with respect to ground.
FIG. 2
of the accompanying drawings illustrates another known level shifting circuit which is more tolerant of high transistor threshold voltages. This type of arrangement is known as a differential current mirror sense amplifier and is disclosed, for example, in N.West and K.Eshragian, “Principal of CMOS Design”, Addison Wesly, 1993. The circuit comprises a differential pair of n-channel transistors
7
and
8
whose gates are connected to complementary input terminals INB and IN, respectively, and whose sources are connected to a tail current source comprising an n-channel transistor
9
whose gate is connected to a bias voltage source Vbias and whose source is connected to a power supply line vss. The drains of the transistors
7
and
8
are connected to a current mirror formed by p-channel transistors
10
and
11
connected to a further supply line vddd and the drain of the transistor
7
forms the output OUT of the circuit. However, this type of circuit is unable to provide a high degree of level shifting, especially for a digital logic signal where one logic level remains unshifted.
U.S. Pat. No. 5,729,154 discloses another known type of level shifter which is more suitable for poly-silicon integration technology and which is illustrated in
FIG. 3
of the accompanying drawings. The circuit comprises an n-channel transistor
12
whose source is connected to an input IN and whose drain is connected to the drain of a p-channel transistor
13
, whose source is connected to a supply line vddd. Another n-channel transistor
14
has a source connected to a supply line vss and a gate and drain connected together and to the gate of the transistor
12
and to the drain of a p-channel transistor
15
, whose source is connected to the supply line vddd. The gates of the transistor
13
and
15
are connected to the supply line vss. The drains of the transistors
12
and
13
are connected to a conventional complementary transistor inverter comprising transistors
16
and
17
and whose output forms the output OUT of the level shifting circuit.
A disadvantage of this arrangement is that it has a relatively high current consumption. In particular, the transistors
14
and
15
form a path between the supply lines vddd and vss which conducts current continuously. Also, when the input signal to the source of the transistor
12
is a logic low level signal, there is a further path through the transistors
12
and
13
between the supply lines. In order to avoid phase delays between the input and the output signals of the level shifting circuit, the circuit must operate at high speed. This requires relatively large currents and results in a relatively large power consumption.
GB 2 360 405 discloses level shifting circuits which are capable of operating at high speed and with relatively low power consumption.
FIG. 4
of the accompanying drawings illustrates one example of such a circuit which comprises an n-channel transistor
18
and a p-channel transistor
19
. The source and gate of the transistor
18
are connected to a signal input IN and an enable input EN, respectively, whereas the drain of the transistor
18
is connected to an output terminal OUT. The transistor
19
has a gate connected to a supply line vss, a source connected to another supply line vddd and a drain connected to the output terminal OUT.
When the enable signal at the enable input EN is active, the gate of the transistor
18
is biased to a voltage higher than its threshold voltage relative to the supply line vss. The transistor
19
is biased so as to be on but is more “weakly” conductive than the transistor
18
. When the input signal at the input IN is at a low level (at or near the potential of the supply line vss), the transistor
18
is turned on and conducts more strongly than the transistor
19
so that the output is pulled to a low level. Conversely, when the input signal is at a higher level, the transistor
18
is turned off and the output OUT is pulled towards the voltage of the supply line vddd by the transistor
19
. When the circuit is disabled, the transistor
18
is turned off and the output OUT is pulled towards the voltage of the supply line vddd by the transistor
19
.
FIG. 5
of the accompanying drawings illustrates a modified form of the level shifting circuit shown in
FIG. 4
in which the enable input EN is also connected to the input of an inverter
20
whose output is connected to the gate of the transistor
19
and to a pull-down transistor
21
. In this case, when the circuit is disabled, the transistor
19
is switched off and the pull-down transistor
21
pulls the output OUT towards the voltage of the supply line vss.
FIG. 6
of the accompanying drawings shows another form of the level shifting circuit of GB 2 360 405. The gate of the transistor
18
is connected to the gate and drain of an n-channel transistor
22
whose source is connected to the supply line vss. The source and drain of the transistor
22
are connected to the drain of a p-channel transistor
23
whose source is connected to the supply line vddd and whose gate is connected to the gate of the transistor
19
and to the enable input EN. The enable input EN is connected to the gate of the pull-down transistor
21
and to the gate of another pull-down transistor
24
connected across the transistor
22
.
This arrangement provides more accurate biasing of the “pass gate” transistor
18
and provides a higher degree of level shifting. When the circuit is enabled, the transistors
22
and
23
bias the gate of the transistor
18
just above its threshold voltage. When the circuit is disabled, the pull-down transistor
24
is turned on and the gates of the transis
Brown Christopher James
Cairns Graham Andrew
Cho James H.
Renner , Otto, Boisselle & Sklar, LLP
Sharp Kabushiki Kaisha
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