Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-08-13
2004-09-28
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S426000, C438S221000, C438S296000, C438S297000, C438S450000
Reexamination Certificate
active
06797587
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for fabricating semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced performance, semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication is the fabrication and use of isolation regions which isolate semiconductor devices formed within adjacent active regions within a semiconductor substrate. While isolation regions are thus desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, isolation regions are nonetheless not formed entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device and isolation region dimensions have decreased, it has become increasingly more difficult to fabricate semiconductor integrated circuit microelectronic fabrications such that isolation region fabrication methods minimally affect semiconductor devices formed within adjacent active regions within a semiconductor substrate.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to fabricate semiconductor integrated circuit microelectronic fabrications such that isolation region fabrication methods minimally affect semiconductor devices formed within adjacent active regions within a semiconductor substrate.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, isolation regions within semiconductor substrates.
Often, such methods may be directed towards materials considerations when forming isolation regions within semiconductor substrates. Representative among such methods, but not limiting among such methods, are methods disclosed within Puchner et al., in U.S. Pat. No. 6,156,620 and Huang et al., in U.S. Pat. No. 6,323,106, the disclosures of which are incorporated herein fully by reference.
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods for forming within semiconductor substrates isolation regions such as to minimally affect semiconductor devices formed within adjacent active regions within the semiconductor substrates.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming an isolation region within a semiconductor substrate.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the isolation region is formed such as to minimally affect semiconductor devices formed within active regions adjacent the isolation region within the semiconductor substrate.
In accord with the objects of the present invention, there is provided by the present invention a method for forming an isolation region within a semiconductor integrated circuit microelectronic fabrication. To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed over the semiconductor substrate an isolation trench mask layer which defines the location of an isolation trench to be formed adjoining an active region of the semiconductor substrate. There is then etched the semiconductor substrate, while employing the isolation trench mask layer as an etch mask layer, to form the isolation trench adjoining the active region of the semiconductor substrate. There is then laterally etched the isolation trench mask layer to form a laterally etched isolation trench mask layer which uncovers a corner of the active region of the semiconductor substrate adjoining the isolation trench. There is then implanted into the corner of the active region, while employing the laterally etched isolation trench mask layer as an ion implantation mask layer, a dose of a dopant such as to provide a corner implanted active region. Finally, there is then formed into the isolation trench adjacent the corner implanted active region an isolation region.
The present invention provides a method for forming an isolation region within a semiconductor substrate, wherein the isolation region is formed while minimally affecting semiconductor devices formed within active regions adjacent the isolation region within the semiconductor substrate.
The present invention realizes the foregoing object by, prior to forming an isolation region within an isolation trench formed adjoining an active region of a semiconductor substrate, implanting a dopant into a corner of the active region uncovered by laterally etching an isolation trench mask to form a laterally etched isolation trench mask which serves as an ion implantation mask layer when implanting the dopant into the corner of the active region.
REFERENCES:
patent: 6156620 (2000-12-01), Puchner et al.
patent: 6323106 (2001-11-01), Huang et al.
patent: 6569747 (2003-05-01), Achuthan et al.
patent: 2003/0022426 (2003-01-01), Kumamoto
patent: 2003/0042546 (2003-03-01), Abbott
patent: 2004/0005764 (2004-01-01), Wu et al.
Lin Chung-Te
Sheu Yea-Dean
Wang Chih-Hung
Yang Feng-Cheng
Taiwan Semiconductor Manufacturing Co. Ltd
Tran Thanh Y.
Tung & Associates
Zarneke David A.
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