Method of patterning dielectric layer with low dielectric...

Details Method of patterning dielectric layer with low dielectric... Method of patterning dielectric layer with low dielectric...

2002-04-09

2004-04-06

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S633000, C438S638000, C438S700000, C438S949000

Reexamination Certificate

active

06716741

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of patterning a dielectric layer. More particularly, the present invention relates to a method of patterning a dielectric layer with a low dielectric constant k.
2. Description of Related Art
For the high speed integrated circuitry, the dimensions of semiconductor devices become smaller and interconnect pitch density becomes higher. For a common dielectric layer, for example, a silicon oxide layer, due to its high dielectric constant, a high RC delay is easily caused. Therefore, it is common to apply a low dielectric constant (low-k) dielectric layer as an inter-metal dielectric (IMD), which has the advantage such as reducing the interconnection parasitic capacitance, consequently reducing the RC delay, or mitigating the cross talk between metal lines, hence, the operation speed is improved.
In order to further reduce the RC delay and enhance the operation performance, copper, having low resistance, high melting point and high resistance of electromigration, in used in combination with the low-k dielectric layer. Copper wiring lines not only reduce RC delay but also reduce the static capacitance between wiring lines.
Because the etching step of copper metal is difficult to control, a damascene process is usually used to fabricate copper lines and copper plugs.
In the conventional via-first damascene process for forming a copper damascene plug structure, as shown in
FIG. 1
, a cap nitride layer
102
is formed over metal interconnects (not shown) within a provided substrate
100
. Afterwards, a first low-k dielectric layer
104
, a stop layer
106
, a second low-k dielectric layer
108
, a chemical mechanical polishing (CMP) stop layer
110
and a bottom anti-reflection coating (BARC) layer (not shown) are formed in sequence on the cap nitride layer. Then, a patterned first photoresist layer is formed on the BARC layer for defining vias. By using the first photoresist layer as a mask and the cap nitride layer is used as an etching stop layer, a first anisotropic etching process is performed through the layers to form a via opening (not shown).
After removing the first photoresist layer, a gap filling process is performed to fill the via with a polymer material layer to protect the cap nitride layer. After a patterned second photoresist layer is formed on the polymer material layer, a second anisotropic etching process is performed to define a trench opening (not shown), by using the stop layer as an etching stop layer.
Next, a barrier layer
120
is formed on the via opening and the trench opening. Then, a conductive layer
130
is formed on the barrier layer
120
and fills the openings. Then, chemical mechanical polishing (CMP) is performed to accomplish the conventional damascene process.
FIG. 1
shows a prior-art copper damascene plug structure manufactured by the cited above process.
However, the polymer material layer covering the via opening provokes a fence profile around top of the via opening. It is because the polymer material layer hinders the etching, resulting in incomplete removal of the second low-k dielectric layer
108
.
Furthermore, while the second photoresist layer is subsequently stripped by a photoresist removal process, such as a nitrogen/oxygen plasma ashing process or a nitrogen/hydrogen plasma process, the performed photoresist removal process usually damages the side walls of the second dielectric layer
108
, leading to dielectric constant shift of the low-k dielectric layer and increased leakage current. Moreover, the low-k dielectric material of the damaged sidewalls tends to absorb moisture, resulting in poor adhesion and degradation in the follow-up metallization process.
SUMMARY OF THE INVENTION
In light of foregoing, the invention provides a method of patterning a dielectric layer with a low dielectric constant k without provoking damages to the low-k dielectric layer, thereby avoiding poisoned plugs and degradation of metallization. Moreover, the present invention has no need of using photoresist layers for patterning the low-k dielectric layer, thus preventing the remaining residue and incomplete removal problems.
The present invention uses a high energy flow to directly pattern the low-k dielectric layer without using photoresist layers as masks in the photolithography steps. The high energy flow includes x-rays, electron beams, ion beams or any other electromagnetic waves with high energy.
As embodied and broadly described herein, the invention provides a method for patterning a low-k dielectric layer by direct exposure to a high energy flow, so that the exposed portion of the low-k dielectric layer is cured and becomes insoluble to the developing solution. The unexposed portion of the low-k dielectric layer is soluble to the developing solution and will be removed in the developing process.
By not using any photoresist layer in the photolithography process, the low-k dielectric layer is patterned directly by the high energy flow, thus preventing the low-k dielectric layer from being damaging and avoiding the poison plug problems. The performance and reliability of the device are improved and the fabrication processes are simplified.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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