Semiconductor memory device post-repair circuit and method

Details Semiconductor memory device post-repair circuit and method Semiconductor memory device post-repair circuit and method

2002-05-30

2004-03-09

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06704228

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains generally to semiconductor memory device repair structures and repair methods, and more particularly to post-repair structures and methods.
2. Description of the Related Art
Semiconductor memory devices, e.g., Dynamic Random Access Memory (DRAM) devices, contain a plurality of memory cells arranged in a row/column array. Each memory cell typically stores one bit of information. The array contains row signal lines, and column signal lines arranged perpendicular to the row lines. A memory cell is placed at each intersection of a row line and a column line. Concurrently addressing the array row line and the array column line that connect to a particular memory cell accesses that memory cell.
Most uses for semiconductor memory devices require that 100% of the memory cells, row lines, and column lines be operational. In practice, many—even most—main memory cell arrays on a given wafer may fail to achieve 100% operability. Consequently, most device designs incorporate a relatively small redundant array of memory cells that can be substituted for a limited number of defective cells.
In one common design, the redundant array is configured in redundant columns of memory cells, each connected to a redundant column line that crosses the main memory cell array row lines. Each redundant column line can therefore be substituted for a main memory cell array column found to have one or more defective cells. Each time a column of the main array is addressed, a redundancy control block compares the column address to the defective column address. When the defective column is addressed, the redundancy control block selects the redundant column associated with that defective column address instead.
A redundancy scheme that replaces defective rows with redundant rows is also in use. Some devices contain redundant rows and redundant columns, with associated circuitry.
Before a redundancy control block and its associated redundant column/row can be used, the defective line address must be programmed into the control block. To facilitate programming, the redundancy control block contains a fuse block. While the semiconductor memory device is in a wafer state, the main memory array is tested and defective cells are located. Considering, e.g., column replacement, a redundancy control block and redundant column are selected to replace a given defective column. The address of the defective column is set in the redundancy control block by selectively cutting fuses in the fuse block to represent that column address. Fuses are generally programmed using a laser beam to physically sever each fuse to be cut.
SUMMARY OF THE INVENTION
Although most memory array defects are detectable during wafer state testing, some defects may arise—or first become apparent—after a memory device is packaged. For such defects, the ability to repair the memory array after packaging may make the difference between a saleable unit and a scrap unit.
The repair of array defects after packaging is referred to as a post-repair capability. Laser-cut fuses do not have post-repair capability, as the packaging material prevents laser targeting and fuse cutting. In contrast, the described embodiments all contain a post-repair capability that uses electrically programmable fuse blocks. Such fuse blocks can be programmed after device packaging, using special programming command signaling applied to the device's normal package connections.
Although post-repair redundancy is attractive because it allows the correction of defects that arise during packaging, such redundancy does have drawbacks. The post-repair redundancy control block and associated electrical programming circuitry require much more circuit area than a laser-cut fuse redundancy control block. Therefore, the cost of using electrically cut fuses rather than laser-cut fuses, in terms of wafer surface area, may outweigh the benefit of a post-repair capability.
In a first aspect of this description, a semiconductor memory device is disclosed. The memory device contains a dual-mode redundancy circuit that blends the advantages of wafer-state (e.g., laser-cut) fuse programming with the advantages of post-repair programming. This circuit contains a plurality of redundant memory lines (e.g., additional column or row lines, each addressing redundant cells). Each redundant memory line is associated with an attendant redundancy control block. The majority of the redundant control blocks contain laser fuse blocks, and can only be programmed prior to assembly of the memory device into a package. At least one of the redundant control blocks, however, contains an electrically programmable fuse block, and is capable of being programmed after assembly of the memory device into a package. Accordingly, such a device allows a dual-cycle repair method: most device repairs are made in the wafer state, with more economical laser fuse blocks; a small number of electrical fuse blocks are available and addressable after package assembly, however, in a post-repair mode, in case, e.g., packaging-related defects occur.
The above design has some redundant memory lines dedicated for laser repair, and some redundant memory lines dedicated for post repair. If a redundant memory line that is dedicated for post repair is itself defective, post repair becomes impossible. This is true even if good redundant laser-repair memory lines remain unused, as those lines cannot be used for post repair.
Thus, in a second aspect, a dual-mode redundancy circuit contains circuitry for increasing the likelihood that post repair can be effected. Generally, this circuitry allows a wafer-state address-storage-unit (e.g., a laser fuse block) to be associated with a redundant line. In a second configuration, this circuitry allows a post-repair address-storage-unit (e.g., an electric fuse block) to be associated with the same redundant line. Thus, a semiconductor memory device employing this type of dual-mode redundancy allows additional repair flexibility. For instance, during wafer-state testing, by default each redundant line may be associated with a laser fuse block. One defect-free redundant memory line is designated, during testing, for use in post repair. That redundant memory line is associated with the post-repair address-storage-unit, making it available for use in post repair.
In a related method, the semiconductor device has multiple redundant memory lines, each associated with a laser fuse/comparator. Main and redundant memory lines are tested to determine which lines are defective and which are defect-free. For each defective main memory line, a defect-free redundant memory line is designated, and the laser fuse/comparator associated with that redundant memory line is configured to replace the defective main memory line. When at least one defect-free redundant memory line remains undesignated after this step, at least one remaining defect-free redundant memory line is designated for use in post repair. The post-repair-designated redundant memory line is associated with a post-repair comparator instead of its associated laser fuse/comparator, and is then available for post repair.


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