Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-10
2004-03-23
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S283000, C438S195000, C438S129000, C257S288000
Reexamination Certificate
active
06710414
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to MOS-gated devices, and to methods for making the same.
BACKGROUND OF THE INVENTION
A large number of surface geometries have been developed for use in the manufacture of MOS-gated devices. These surface geometries or “layouts” include interdigitated structures as well as repeating or “cellular” structures, including the well-known hexagonal geometry exemplified by HEXFET® power MOSFETs. These various surface geometries have been developed to optimize device characteristics such as on-resistance and ruggedness. For a given geometry and voltage, the on-resistance of the device is inversely proportional to the active device area. To design a new device with a desired on-resistance using an existing surface geometry, only the product of the on-resistance of an existing device multiplied by its active area needs to be calculated. Based on this information, the active area of the new device is determined, the overhead for pads and termination is added, and the device with the desired on-resistance can be manufactured.
However, the conventional approach of producing a new set of masks for each different on-resistance value or each different size of the MOS-gated device is undesirable in that it can result in the generation of a large number of mask sets for devices that differ primarily in their on-resistance and in the size of their active areas. Moreover, each of these devices must be separately qualified before being shipped to customers. Conventional devices also do not provide an easy means by which gate and source pads can be moved to accommodate a particular end-use.
There is thus a need in the art for a method for producing MOS-gated devices that requires only a single set of masks to be produced, and that can use the same set of masks to make MOS-gated devices of varying sizes and having different on-resistances. There is also a need in the art for a method for making MOS-gated devices such that a family of such devices can be qualified, without having to qualify each particular device within the family. Finally, there is a need in the art for a surface design for MOS-gated devices that allows gate and source pads to be easily moved around within the device so as to accommodate particular end-uses, without requiring substantial re-engineering efforts. These and other needs are met by the methods and devices disclosed herein.
SUMMARY OF THE INVENTION
Modular surface geometries for a MOS-gated device, and methods for using these surface geometries to make MOS-gated devices, are disclosed herein. These modular surface geometries allow the device size to be varied along both the x-axis and the y-axis by predetermined increments.
In some embodiments of the devices and methodologies disclosed herein, the actual device size is set or “programmed” by the contact, metal and pad masks, while in other embodiments the device size is programmed by just the metal and pad masks. This approach saves both time and expense, since only new contact, metal and pad masks, or new metal and pad masks, are required for each new device. Moreover, the wafers which are to be employed in these devices may be prefabricated and stored at an inventory location prior to contact or metal mask, thus allowing a substantial portion of the manufacturing process to be conducted before the specifics of the device are known. This, in turn, significantly reduces the time required to manufacture new devices.
It is also possible to qualify a family of devices made using this approach without qualifying each specific device. In addition, the location of the source and gate bonding pads may be easily moved for assembly in a new package or for a new application. Hence, this approach provides a convenient alternative to producing a new complete set of masks for each new device required.
In one aspect, a method for making a MOS-gated device is disclosed herein. In accordance with the method, a plurality of discrete tiles is provided, each of which has at least one source region and at least one body region. Each tile will also typically have a number of gate contact regions disposed thereon. The plurality of tiles are assembled into an array so as to form a MOS-gated device. Preferably, the tiles are essentially identical in dimension. It is also preferred that the tiles are rectangular or square in shape. A gate metallization layer, which may be, for example, a series of discrete metal traces, is disposed over at least a portion of the array such that it is in electrical contact with the gate contact regions within the array. A source and body metallization layer is disposed over at least a portion of the array such that it is in electrical contact with the source and body regions of the tiles. A termination metallization layer may also be disposed over the tiles which form the outer perimeter of the device, and is typically disposed over these tiles such that it is typically in electrical contact with both the gate contact regions and the source and body contact regions of the outer perimeter tiles.
In another aspect, a MOS-gated device is disclosed herein which comprises an array of discrete tiles, wherein each tile in said array has source regions, body regions, and gate contact regions. A source and body metallization layer is provided which is in electrical contact with the source and body regions of at least two tiles in said array, and a gate metallization layer is provided which is in electrical contact with the gate contacts of at least two tiles in said array. Preferably, each tile in the array has four gate contact regions, at least two of which are in contact with the gate metallization layer for tiles disposed in the interior of the array. The tiles are typically disposed in the array such that a gap exists between adjacent tiles, and the source and body metallization layer preferably extends over this gap. The gate metallization layer and the source and body metallization layer will typically be electrically insulated from each other, as by maintaining a physical gap or space between them. The tiles in the array may have a trench or a planar structure.
In still another aspect, a MOS-gated device is provided herein which comprises an array of discrete tiles. The array includes a first plurality of tiles disposed along the exterior of the array, and a second plurality of tiles disposed within the interior of the array. Each of the first and second plurality of tiles has a source and body region and a gate contact region. The device further includes a source and body metallization layer which is in electrical contact with the source and body regions of the first and second plurality of tiles, and a termination metallization layer which is in electrical contact with at least one source and body region and at least one gate contact region on each of said first plurality of tiles.
These and other aspects of the methods and devices disclosed herein are described in further detail below.
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David Mavis et al., “A Reconfigurable, Nonvolatile, Radiation Hardened Field Programmable Gate Array (FPGA) for Space Applications,” 10pp. www.APLDCon98/Papers/b8_mavis.pdf.
Charles W. Stirk et al., “Manufacturing Cost Analysis of Integrated Photonic Packages,” Bosonics, Inc., 1472 North St., Boulder, CO 80304, presented Jan. 22, 1999.www.spie.org/web/meetings/programs/pw99/confs/3631B.html.
“The Do's and Don'ts of Using MOS-Gated Transistors,” 7pp.www.eetkorea.com/ARTICLES/2000MAY/2000MAY04_BD_BT_AN.PDF.
Everhart Caridad
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Williams Esq. Karin L.
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