Cache/smartcache with interruptible block prefetch

Details Cache/smartcache with interruptible block prefetch Cache/smartcache with interruptible block prefetch

2001-08-17

2004-01-13

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06678797

ABSTRACT:

This application claims priority to European Application Serial No. 00402331.3, filed Aug. 21, 2000 and to European Application Serial No. 01400685.2, filed Mar. 15, 2001. U.S. patent application Ser. No. 09/932,651 is incorporated herein by reference.
FIELD OF THE INVENTION
This invention generally relates to microprocessors, and more specifically to improvements in cache memory and access circuits, systems, and methods of making.
BACKGROUND
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first aspect of the invention, there is provided a digital system having at least one processor, with an associated multi-segment memory circuit. Validity circuitry is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds a valid data value. Block transfer circuitry is connected to the memory circuit and is operable to transfer a block of data to a selected portion of segments of the memory circuit such that a transfer to any segment within the selected portion of segments holding valid data is inhibited.
Another aspect of the present invention provides a method of operating a digital system having a processor and memory circuit. A block transfer to a selected plurality of segments in the memory circuit is initiated. During the block transfer, each segment is tested to detect if a segment within the selected plurality of segments holds valid data. A transfer within the block transfer to a segment is inhibited if the segment contains a valid data value.
Another aspect is that valid data can be transferred to a segment by a single data or instruction operation after a block transfer is initiated. In this case, a transfer within the block transfer to the segment is inhibited if the segment contains a valid data value.


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IBM Technical Disclosure Bulletin,Prefetching With Invalid Cache Entries, vol. 33, No. 3B, Aug. 1, 1990, p. 46; IBM Corp., New York, NY, US.
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