Polishing of conductive layers in fabrication of integrated...

Details Polishing of conductive layers in fabrication of integrated... Polishing of conductive layers in fabrication of integrated...

2002-11-13

2004-03-30

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

Reexamination Certificate

active

06713782

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to mechanical or chemical mechanical polishing of conductive layers.
Chemical mechanical polishing (CMP) have been used to pattern metal layers in fabrication of semiconductor integrated circuits.
FIGS. 1 and 2
illustrate cross sections of a wafer in one fabrication process. The fabrication starts with a semiconductor substrate
120
. MOS transistor source/drain regions
130
are formed in substrate
120
, and a transistor gate
140
is formed over a channel region extending between the source/drain regions. (Other circuit elements may also be present) A dielectric
150
is formed over the substrate
120
and patterned as needed. A conductive layer
160
(e.g. aluminum) is formed on dielectric
51
and suitably patterned. A dielectric
170
is formed on layer
160
. Trenches
184
are etched in dielectric
170
to define interconnect lines. Vias
190
are etched at the bottom of the trenches at selected locations to expose the layer
160
. Then a metal layer
194
(tungsten or copper) is deposited over the structure, filling the trenches
184
and the vias
190
.
The wafer is polished by CMP (
FIG. 2
) until the metal
194
is removed from the top surface of dielectric
170
. Trenches
184
and vias
190
remain filled with metal
194
, providing he interconnect lines contacting the layer
160
in vias
190
.
To ensure complete removal of metal
194
from the top surface of dielectric
170
, the wafer is overpolished, i.e. the polishing continues for some time after the dielectric
170
is exposed. When the dielectric has been exposed, the polishing proceeds faster in a region
210
having a high density of metal lines
194
, than in a surrounding region
220
having no metal lines. Consequently, the top surface of region
210
is indented (“eroded”). The erosion undesirably changes the electrical properties of interconnect lines
194
. Also, the top surface of the wafer becomes non-planar, which complicates fabrication of overlying layers. See U.S. Pat. No. 6,340,602 issued Jan. 22, 2002 to Johnson et al. and incorporated herein by reference.
In order to ensure that the erosion does not exceed some acceptable limit, the polished wafers are examined to determine the maximum erosion value &Dgr;. If &Dgr; exceeds the limit, the wafer is discarded. Also, if &Dgr; approaches or exceeds the limit, the CMP process is adjusted to reduced the erosion in subsequent wafers.
The maximum erosion &Dgr; can be measured with a probe tool
230
, e.g. a stylus profilometer or a scanning probe microscope (e.g. atomic force microscope). Tool
230
has a probe
240
, a circuitry
250
for processing the data from the probe, and a mechanism (not shown) for moving the probe relative to the wafer. See e.g. U.S. patent application publication No. 2001/0047682 published Dec. 6, 2001. Probe
240
contacts the wafer top surface, or comes very close to the wafer to sense the top surface topography. Undesirably, the wafer can be contaminated by the probe. Therefore, more expensive and complicated optical instruments have been used instead of the probe instruments to measure the erosion in production wafers.
SUMMARY
The invention is defined by the appended claims which are incorporated into this section by reference. This section summarizes below some features of the invention.
Some embodiments of the invention make it safer to use a probe for the erosion measurements on production wafers. This will now be illustrated with reference to
FIG. 3
, showing the top view of a polished wafer. In this example, trenches
184
and metal lines
194
form a periodic pattern in region
210
. The pattern has a pitch P defined as a distance between similar points on the adjacent metal lines. P=W+S, where W is the width of each metal line and S is the distance between the adjacent lines
194
. It is well known that the erosion increases with the W/P ratio.
The inventor has studied the dependence of the erosion on the size of regions
210
, and has discovered that if the W and S parameters are held constant, then the size dependence is weak. Consequently, the erosion in a large region
210
can be estimated by measuring the erosion of a smaller test structure. For example, a test structure of 50×50 &mgr;m can be incorporated into the wafer and used to monitor the erosion in a region
210
having dimensions on the order of several millimeters (e.g. the lines
194
can be bitlines or strap lines of a memory array). The erosion of the test structure can be measured with a probe tool
230
since damage to the test structure is acceptable. The probe may contact the wafer, or come as close as 2 &mgr;m to the wafer, or as close as 1 &mgr;m, or closer. &Dgr;test structure of 50×50 &mgr;m can be formed on a scribe line or a margin of the wafer.
In some embodiments, the test structure has the same layers (e.g.
150
,
160
, etc.) as the actual circuitry region
210
In other embodiments, some layers (e.g.
140
or
160
) are omitted in the test structure. Also, the test structure may have additional layers.
The invention is not limited to the embodiments described above. The invention is not limited to rectangular regions
210
or periodic structures. For non-periodic structures, the pitch P is defined as the distance between the corresponding points on the adjacent metal lines (e.g. between the left edges of the adjacent lines), and the pitch P may vary over the structure. Also, the invention is not limited to use of a probe to measure the erosion. Some aspects of the invention consist in the presence of certain structures on the wafer and are not limited to the use of a probe. The erosion of the wafers with such structures can be measured with optical instruments without a probe. Other features of the invention are described below. The invention is defined by the appended claims.


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patent: 5874318 (1999-02-01), Baker et al.
patent: 5972798 (1999-10-01), Jang et al.
patent: 6087733 (2000-07-01), Maxim et al.
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 6292265 (2001-09-01), Finarov et al.
patent: 6300248 (2001-10-01), Lin et al.
patent: 6340602 (2002-01-01), Johnson et al.
patent: 6472291 (2002-10-01), Page et al.
patent: 6486066 (2002-11-01), Cleeves et al.
patent: 2001/0015811 (2001-08-01), Ravid et al.
patent: 2001/0047682 (2001-12-01), Samsavar et al.
patent: 2002/0076867 (2002-06-01), Lee et al.
patent: 2002/0106837 (2002-08-01), Cleeves et al.

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