Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-10-10
2004-05-11
Vigushin, John B. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S778000, C257S786000, C257S787000, C361S768000, C361S771000
Reexamination Certificate
active
06734540
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the packaging of semiconductor devices. More particularly, this invention relates to a large semiconductor device package that minimizes the impact of different coefficients of thermal expansion associated with the environment in which the package exists. The invention also relates to processing techniques employed for under-filling of chip dies to thin substrates which require rigid stiffeners to control the flatness of the device packages and reduce bowing affects due to internal stresses caused, for example, by differences in coefficients of thermal expansion between material layers.
DESCRIPTION OF THE RELATED ART
Integrated circuit geometry is becoming smaller, resulting in higher performance and functionality per unit area. While the chip circuitry is becoming more dense, the chip area is becoming larger and larger. Many of today's chips have hundreds, and even thousands of pads, that must be electrically connected to interface with a printed circuit board (PCB) containing other electrical elements and chips. It is important that the chip connections be designed in such a way as to allow for the chip pads to interconnect with the package.
As chips contain more functions that require a connection to the package, the bond pad area at the chip perimeter is beginning to exceed the capability of current technology to make connections from the chip to the package using traditional wire bond techniques. Wire connections from these pads to the package are limited by pad pitch and size. To overcome such limitations, the makers of integrated circuits are employing techniques to redistribute the pads to locations within the outer perimeters of chips, and converting the connection techniques from wire bonding to soldering the pads directly to the package. This technique is referred to as “flip chip” technology. While this technology has been in existence for many years, what is now unique to this technology is the shear magnitude of the die size and the number of interconnects. It is now possible to produce die sizes in excess of 35 mm square with thousands of interconnects.
The placement of semiconductor devices onto a substrate, or a printed circuit board, is generally referred to as the die placement, die attach or die bonding operation. Die placement techniques vary depending on the assembly process used. Variations in the technique can be due to a variety of design considerations, such as the particular application of the semiconductor package or the method necessary to interconnect the die within the package.
A common method of interconnecting the die within the package is wire bonding. In wire bonding, a wire is bonded both to the die circuitry and bonded to the substrate. In another method, the “flip chip” approach, a semiconductor die, referred to as a “bumped” die, includes patterns of contact bumps formed on a face of the die. The bumps are solder balls on the underside of the chip that are registered or aligned with solder pads on the substrate.
The bumps allow the die to be mounted to a substrate and act as mechanical and electrical contact points with integrated circuit (ICs) formed on the die. The bumped device is mounted to the substrate active side down. Since the active circuitry is facing down instead of up, as in the case for wire bonded devices, this approach is known as “flip chip”. This mounting process was originally developed by IBM and is also known as the C4 joining process (Controlled Collapse Chip Connection). In other structures, a silicon chip is embedded in the packaging where a top layer of bumps is not required.
Considering that the chip is in intimate contact with the package surface material, it is important that the chip surface and the package mounting surface have similar mechanical properties, so as to reduce the stress conditions between the chip and the package. Different package materials have different mechanical properties, such as different coefficients of thermal expansion, or “CTE”. As the die size increases, the CTE between the chip and the package causes increased stress. If this stress increases above the modulus of the materials, there can be fatigue failure at the connection between the chip and the package.
In addition to the CTE differences between the chip and the package materials, there are other mechanical conditions to consider, such as the internal stresses of the package materials that cause bowing of the package. Extreme bowing can prevent the attachment of the die to the substrate, or the substrate to the printed circuit board.
Traditionally, small flip chips (less than 15 mm) have been mounted to single or multi-layer organic substrates, similar to printed circuit boards. Since the CTE of the chip is low (i.e., less than 3 parts per million (PPM)), and the CTE of an organic substrate is high (i.e., in the range of 14 to 17 PPM), a large die (e.g., greater than 26 mm) mounted directly to this type of substrate would be under a very high stress during certain temperature cycles. Ideally, a package must perform over a temperature range of greater than 100 degrees Celsius. For a temperature range of this type, the joint of a soldered connection between the chip and the substrate will fail due to thermal fatigue in less than 500 temperature cycles.
To improve the mechanical performance between a chip and a printed circuit board, glass, ceramic and glass-ceramic mounting layers have been used. These materials, generally referred to as glass-ceramic materials, have coefficients of thermal expansion in the range between 3 and 7 PPM (parts per million) and therefore more closely match the CTE of the semiconductor. This match in CTE lowers the chip-to-substrate stress and allows the chip connection to maintain a bond during temperature cycling. However, this approach results in a secondary problem when the package is mounted to a printed circuit board with a CTE greater than the glass-ceramic CTE. The problem of early temperature cycling failure is now transferred from the die-to-package interface, to the package-to-board interface. Some manufacturers have overcome this secondary problem by employing what is know as “column grid array” connections, but this technique does not lend itself to more conventional socket and board mounting requirements.
Metal alloys (e.g., a lead tin alloy for example) can be used to form the bumps. Typically, the bumps are dome shaped, and have an average diameter of from 5 mils to 30 mils or greater. Micro ball grid arrays (BGA) are formed in the smaller range, while standard ball grid arrays are formed in the larger size range. The sides of the bumps typically bow or curve outwardly from flat top surfaces. The flat top surfaces of the bumps form the actual regions of contact with the mating contacts on the substrate.
Referring to
FIGS. 1-3
, a semiconductor die or flip chip
20
is provided with a pattern of solder bumps
22
on an underside or circuit side of the chip. The solder balls
22
align with solder pads
24
on a PC board or similar substrate
26
. Flux is normally applied between the solder balls
22
and solder pads
24
. Upon heating, the solder pads
24
on the substrate
26
reflow and physically connect with the solder balls
22
on the underside of the chip
20
. High lead solder balls
22
typically have a high melting point and therefore do not reflow; eutectic solder balls would melt and slightly collapse and reflow onto the printed circuit board pads. This connection is illustrated in
FIG. 2
by deformed solder pad
24
′ mating with a solder ball
22
. This process eliminates the requirement for wire bonding.
Special liquid epoxy
28
(
FIG. 3
) is typically used to completely fill the underside of the chip. This is referred to herein as the “underfill” operation. Upon curing, the resulting encapsulation forms a barrier to prevent moisture from contacting and thus corroding the electrical interconnects between the substrate
26
and the chip
20
. The epoxy
28
also serves to protect the bonds betwee
Altera Corporation
Vigushin John B.
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