SRAM power-up system and method

Details SRAM power-up system and method SRAM power-up system and method

2003-01-21

2004-05-04

Mai, Son L. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S154000, C365S156000, C365S168000, C365S188000, C365S189110, C365S190000, C365S202000

Reexamination Certificate

active

06731546

ABSTRACT:

TECHNICAL FIELD
This invention relates to static random access memory (“SRAM”) devices, and, more particularly, to a system and method for powering-up SRAM devices having PMOS access transistors to limit the initial current draw of such SRAM devices.
BACKGROUND OF THE INVENTION
Many integrated circuit devices, such as microprocessors, include on-board memory devices, such as SRAM devices. For example, SRAM devices are commonly used as cache memory because of their relatively fast speed. SRAM devices are also sold as stand-alone integrated circuits for use as cache memory and for other uses. SRAM devices are also more suitable for use as cache memory than dynamic random access memory (“DRAM”) devices because they need not be refreshed, thus making all SRAM memory cells continuously available for a memory access.
FIG. 1
is a block diagram of a portion of a typical array
10
of SRAM cells
12
arranged in rows and columns. A plurality of complementary digit line pairs D, D* are used to couple complementary data to and from the memory cells
12
in a respective column. Several digit line pairs, typically 16 or 32 digit line pairs, are coupled to respective inputs of a column multiplexer
13
. The column multiplexer
13
couples one pair of digit lines corresponding to a column address to a sense amplifier
14
and a write driver
16
. The sense amplifer
14
provides a data output (not shown) indicative of the polarity of one digit line D relative to the other D* responsive to data being read from a memory cell
12
coupled to the selected digit line pair D, D*. The write driver
16
drives a differential voltage onto the digit lines D, D* to which the write driver
16
is coupled by the column multiplexer
13
. The differential voltage applied between the digit lines is indicative of data that is to be written to a memory cell
12
coupled to the digit lines D, D*. An equilibration PMOS transistor
18
is also coupled between each pair of complementary digit lines D, D* to equalize the voltage between the digit lines D, D* prior to a memory read operation. Finally, a complementary PMOS bias transistor
20
is coupled to each digit line D, D* to lightly bias the digit lines D, D* to V
cc
for reasons that will be explained. The current provided by each pair of bias transistors is controlled by a respective digit line load signal DLL
N
.
A plurality of word lines WLI-WL
4
are used to activate the memory cells
12
in the respective row of memory cells. The word lines WL
1
-WL
4
are coupled to a respective inverter
30
each formed by a PMOS transistor
34
and an NMOS transistor
36
coupled in series between V
cc
and ground. The gates of the transistors
34
,
36
are coupled to each other and to a respective select line SEL WL
1
-SEL WL
4
.
In a read operation, the digit lines D, D* for all columns are equilibrated by driving an EQ* line low. An inverter
30
then drives a word line WL
1
-WL
4
in a single row to an appropriate voltage, thereby coupling a memory cell
12
in each column to a respective pair of digit lines D, D*. The memory cell
12
in each column unbalances the digit lines D, D* to which it is coupled, and the respective sense amplifier
14
senses the polarity of the unbalance and provides an appropriate data signal.
In a write operation, a suitable voltage is first applied to a word line WL
1
-WL
4
to couple the memory cells
12
in the respective row to a digit line D or a complimentary digit line D*. The write driver
18
for one or more columns then applies a differential voltage between the digit lines D, D* for respective columns, which is coupled to respective memory cells
12
for the activated row. The write driver
18
is then disabled for a “write recovery” phase, and the word line WL
1
-WL
4
is then deactivated so the memory cell
12
stores the polarity of the differential voltage. The bias transistors
20
are provided for the array
10
regardless of the type of SRAM cell used. However, in the event the memory cells
12
are loadless 4T memory cells, which are discussed further below, the current provided by the bias transistors
20
allow the memory cells
12
to continue to store the data, as also discussed further below.
A typical memory cell shown in
FIG. 2
is a conventional 6-transistor (6-T) SRAM cell
40
. The SRAM cell
40
includes a pair of NMOS access transistors
42
and
44
that allow a differential voltage on the digit lines D, D*, to be read from and written to a storage circuit
50
of the SRAM cell
40
. The storage circuit
50
includes NMOS pull-down transistors
52
and
56
that are coupled in a positive-feedback configuration with PMOS pull-up transistors
54
and
58
, respectively. Nodes A and B are complementary inputs/output nodes of the storage circuit
50
, and the respective complementary logic values at these nodes represent the state of the SRAM cell
40
. For example, when the node A is at logic “1” and the node B is at logic “0”, then the SRAM cell
40
is storing a logic “1”. Conversely, when the node A is at logic “0” and the node B is at logic “1”, then the SRAM cell
40
is storing a logic “0”. Thus, the SRAM cell
40
is bistable, i.e., the SRAM cell
40
can have one of two stable states, logic “1” or logic “0”.
In operation during a read of the SRAM cell
40
, a word-line WL, such as WL
1
-WL
4
(FIG.
1
), which is coupled to the gates of the access transistors
42
and
44
, is driven to a voltage approximately equal to V
CC
to turn ON the transistors
42
and
44
. The access transistor
42
then couples the node A to the digit line D, and the access transistor
44
couples the node B to the digit line D*. Assuming the SRAM cell
40
is storing a logic “0”, coupling the digit line D to the node A pulls down the voltage on the digit line D enough (for example, 100-500 millivolts) to cause the sense amplifier
14
(
FIG. 1
) coupled between the digit lines D, D* to read the SRAM cell
40
as storing a logic “0”.
During a write operation of a logic “1” to the SRAM cell
40
, for example, a logic “1” is applied to the digit lines D, D* as a differential voltage, and the word line WL is activated to turn ON the access transistors
42
,
44
. The transistor
42
then couples the logic “1” voltage of approximately V
CC
to the node A, and the transistor
44
couples the logic “0” voltage of approximately ground to the node B. The word line WL is finally deactivated to turn OFF the access transistors
42
,
44
, thereby allowing the SRAM cell
40
to continue storing the logic “1”.
Although the 6-T cell
40
shown in
FIG. 2
uses PMOS pull-up transistors
54
,
58
, it will be understood that other components (not shown), such as pull-up resistors (not shown), may be used in place of the pull-up transistors
54
,
58
.
Another typical SRAM cell is shown in FIG.
3
. The SRAM cell shown in
FIG. 3
is a conventional 4-transistor (4-T) loadless SRAM cell
60
, where elements common to the SRAM cell
40
of
FIG. 2
are referenced with like numerals or letters. The SRAM cell
60
is considered loadless because it uses a storage circuit
66
in which the loads formed by the pull-up transistors
54
,
58
have been eliminated. Further, the NMOS access transistors
42
and
44
have been replaced with PMOS transistors
62
and
64
, respectively. With the loadless 4-T SRAM cell
60
of
FIG. 3
, there are no pull-up transistors to maintain the drain of the OFF NMOS transistor
52
,
56
at a voltage that is sufficient to turn ON the other NMOS transistor
52
,
56
. Instead, the access transistors
62
,
64
are biased in their OFF states by conventional means with a voltage that causes leakage currents and/or subthreshold currents to be coupled from the digit lines D, D* through the access transistors
62
,
64
. These leakage currents and/or subthreshold currents maintain the voltage on the drain of the OFF NMOS transistor
52
,
56
, at a voltage that is sufficiently high to maintain the other NMOS transistor
52
,
56
in an ON condition. In order to supply these leakage currents and/or subthreshold c

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