Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-28
2004-03-09
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000
Reexamination Certificate
active
06703662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device including a floating gate and a control gate, and to a manufacturing method thereof.
2. Description of the Related Art
FIG. 1
is a section view showing a nonvolatile semiconductor memory device of a prior art including a floating gate and a control gate.
In
FIG. 1
, the nonvolatile memory device of the prior art including floating gate
21
and control gate
22
is manufactured by forming element isolation area
24
in silicon substrate
23
, forming tunnel gate oxide film
25
, floating gate
21
, ONO film
26
, and control gate
22
on silicon substrate
23
in this order, and forming gate sections of memory cell transistor
27
and select transistor
28
in the same structure through a lithography technique. Then, ion implantation is performed in self-alignment with the gate sections of memory cell transistor
27
and select transistor
28
used as masks to form N-type diffusion layers
29
, and contact
30
and wiring
31
are formed, thereby forming a desired nonvolatile memory device.
The aforementioned prior art nonvolatile memory device, however, has disadvantages as follows. (1) A memory cell has a large size since the lithography limit determines the interval between a memory cell transistor and a select transistor.
(2) The diffusion layer area between a memory cell transistor and a select transistor exhibits a high resistance due to its large area to reduce a current flowing between a drain and a source when data is read from a memory, making it difficult to perform detection for determination of “0” or “1” of a cell.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new semiconductor device capable of improving the prior art with the aforementioned disadvantages, and specifically, reducing the size of a memory cell area and accurately detecting stored data.
To achieve the aforementioned object, the present invention employs a technical configuration as described below.
Specifically, a semiconductor device of a first aspect according to the present invention comprises:
a memory cell transistor including a floating gate and a control gate;
a select transistor;
side walls formed on the sides of the gates of the memory cell transistor; and
a diffusion layer area formed below the side wall and forming part of the memory cell transistor and the select transistor.
A semiconductor device of a second aspect of the present invention comprises:
a memory cell transistor including a floating gate and a control gate;
a select transistor;
side walls formed on the sides of the gates of the memory cell transistor;
a first diffusion layer area of a first conductive type formed below the side wall;
a second diffusion layer area of the first conductive type formed in an area different from the first diffusion layer area of the first conductive type; and
a gate of the select transistor provided above a channel area between the first diffusion layer area of the first conductive type and the second diffusion layer area of the first conductive type.
A method of manufacturing a semiconductor device comprising a memory cell transistor including a floating gate and a control gate and a select transistor of a first aspect of the present invention comprises at least:
a first step of forming the floating gate and the control gate of the memory cell transistor;
a second step of forming a first diffusion layer area of a first conductive type using the gates of the memory cell transistor formed at the first step;
a third step of forming side walls on the sides of the floating gate and the control gate of the memory cell transistor;
a fourth step of forming a diffusion layer area of a second conductive type using the gates of the memory cell transistor and the side walls;
a fifth step of forming a gate oxide film for the select transistor and forming a gate of the select transistor on the gate oxide film; and
a sixth step of forming a second diffusion layer area of the first conductive type using the gates of the memory cell transistor, the side wall, and the gate of the select transistor.
In a method of manufacturing a semiconductor device of a second aspect of the present invention, the gate of the select transistor is formed to overlap the gate of the memory cell transistor.
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Choate Hall & Stewart
NEC Electronics Corporation
Prenty Mark V.
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