Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-04-25

2004-01-06

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S357000, C326S120000

Reexamination Certificate

active

06674127

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including an SOI substrate, and more particularly relates to a semiconductor integrated circuit including an MOS transistor with a body contact portion.
Recently, a semiconductor integrated circuit, including a logic circuit made up of MOS transistors, has been downsized, so that high-speed operation and low-power consumption have been advanced rapidly. However, as the circuit has been downsized to increase its operating speed, an increased amount of leakage current flows through the MOS transistors, which is contrary to the demand for low-power consumption. Under the circumstances such as these, a trade-off between high-speed operation and low-power consumption becomes more and more inevitable, thus making this problem more and more difficult to solve.
An MTCMOS (multi-threshold CMOS) circuit as shown in
FIG. 6
is one of known means for realizing high-speed operation and low-power consumption.
As illustrated in
FIG. 6
, a known MTCMOS circuit includes: a logic circuit section
160
including low-threshold-voltage transistors
151
; a power line
161
for supplying a supply potential VDD; an internal power line
162
for supplying an internal supply potential VD
1
to the logic circuit section
160
via a high-threshold-voltage transistor
152
; and a ground line
163
for supplying a ground potential Vss to the logic circuit section
160
.
The MTCMOS circuit with this structure realizes high-speed operation by operating the relatively small low-threshold-voltage transistors
151
only when the circuit is powered. On the other hand, when the circuit is in standby mode, the high-threshold-voltage transistor
152
is turned OFF to reduce a standby-mode current and eventually the power dissipated. In this manner, the known MTCMOS circuit realizes high-speed operation by taking advantage of the low-threshold-voltage transistors
151
and, at the same time, removes the drawback, i.e., the increase of the leakage current, by using the high-threshold-voltage transistor
152
.
FIG. 7A
illustrates a cross-sectional structure for the low-threshold-voltage transistor
151
.
FIG. 7B
illustrates a cross-sectional structure for the high-threshold-voltage transistor
152
.
As shown in
FIG. 7A
, the low-threshold-voltage transistor
151
is formed on an n-well
201
a.
The n-well
201
a
is electrically isolated by a shallow trench isolation region (which will be herein referred to as an “STI region”)
202
in a semiconductor substrate
201
of silicon. A gate electrode
203
is formed on the n-well
201
a
and source/drain regions
204
and
205
are defined in the n-well
201
a
to be spaced apart from each other in the gate length direction. A channel region is formed in part of the n-well
201
a
under the gate electrode
203
and is defined by a low-threshold-voltage-setting doped layer
206
. Lower parts of the n-well
201
a
and contact-portion well
201
b
are in contact with each other. A potential at the contact-portion well
201
b
is controllable using a substrate contact electrode
207
.
As shown in
FIG. 7B
, the high-threshold-voltage transistor
152
is formed on an n-well
201
c.
The n-well
201
c
is electrically isolated by an STI region
202
in the semiconductor substrate
201
. A gate electrode
213
is formed on the n-well
201
c
and source/drain regions
214
and
215
are defined in the n-well
201
c
to be spaced apart from each other in the gate length direction. The channel region is formed in part of the n-well
201
c
under the gate electrode
213
and is defined by a high-threshold-voltage-setting doped layer
216
. Lower parts of the n-well
201
c
and contact-portion well
201
d
are in contact with each other. A potential at the contact-portion well
201
d
is controllable using a substrate contact electrode
217
.
However, the known MTCMOS circuit needs to include two types of transistors having mutually different threshold voltages, i.e., the low-threshold-voltage transistors
151
and high-threshold-voltage transistor
152
. Accordingly, when the low- and high-threshold-voltage-setting doped layers
206
and
216
are formed, for example, it is necessary to form masks separately for these two types of transistors in implanting dopants. Thus, fabricating cost rises.
Moreover, to further increase the operating speed, an MTCMOS circuit using an SOI substrate has been researched and developed. However, since an SOI substrate is more expensive than a silicon substrate, the fabricating cost further rises when an SOI substrate is used.
Since the high-threshold-voltage transistor
152
has higher resistance than that of the low-threshold-voltage transistor
151
during the operation, a voltage drop is likely to occur. As a result, the internal supply potential VD
1
, which is a supply potential for the logic circuit section
160
, unintentionally becomes lower than the supply potential VDD. Thus, the low-threshold-voltage transistors
151
in the logic circuit section
160
have their operating speed decreased unfavorably.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to form transistors having mutually different threshold voltages through a single ion implantation process and thereby realize high-speed operation and low power consumption.
To achieve this object, a semiconductor integrated circuit according to the present invention includes: a logic circuit section; and a switching transistor for controlling the operation of the logic circuit section. The logic circuit section and the switching transistor are both formed on the same SOI substrate. Also, the switching transistor is implemented as a partially-depletion-type MOS transistor having a body contact portion. In this case, a threshold-voltage-setting doped layer with the same dopant concentration is formed for both the switching transistor and transistors in the logic circuit section by performing a single ion implantation process. The body contact portion herein means a region for fixing a potential level at the active region of the transistor.
In the inventive switching transistor, when the body contact portion is allowed to be electrically floating, the threshold voltage of the switching transistor becomes substantially equal to that of the transistors in the logic circuit section. But when a predetermined voltage is applied to the body contact portion, the threshold voltage of the switching transistor increases its absolute value. In this case, the transistors in the logic circuit section may have no body contact portion. Alternatively, even if those transistors do have the body contact portions, the contact portions are made electrically floating. Thus, even if those transistors have the same dopant concentration at their channel regions, the switching transistor has a relatively high threshold voltage, whereas the transistors in the logic circuit section have a threshold voltage lower than that of the switching transistor.
Accordingly, even though the threshold-voltage-setting doped layer is formed through a single ion implantation process, the switching transistor can be implemented as a partially-depletion-type transistor with the body contact portion and can have its threshold voltage increased or decreased selectively by applying a predetermined voltage to the body contact portion.
Specifically, a first inventive semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states of the logic circuit section and which has a body contact portion. The partially-depletion-type transistor has a threshold voltage, which is substantially equal to that of the transistors in the logic circuit section when no potential is applied to the body contact portion and which is higher than that of the transistors in the logic circuit section when a potential is applied to the body contact portion.

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