Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-19
2004-03-02
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S302000, C257S303000, C257S304000, C257S305000
Reexamination Certificate
active
06700159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. More specifically, the present invention relates to a semiconductor device comprising trench-isolated transistors and a method for fabricating the same.
2. Description of the Background Art
Semiconductor devices provided with a plurality of transistors isolated by trenches have been widely known, and one such device is disclosed in “A Shallow-Trench-Isolation Flash Memory Technology with a Source-Bias Programming Method” IEDM, pp.177-180, 1996.
FIG. 11
shows a cross sectional view of the prior art semiconductor device disclosed in the above-mentioned literature. Referring to
FIG. 11
, the prior art semiconductor device has a plurality of trenches
101
h
on a silicon substrate
101
. Trenches
101
h
are defined by a surface
101
s
of silicon substrate
101
. Surface
101
s
contains an oxide layer
111
, and a silicon oxide film
112
is formed on surface
101
s
. A polysilicon film
119
is filled into trenches
101
h
in such a manner that polysilicon film
119
is in contact with silicon oxide film
112
, and an oxide layer
117
is so formed as to cover the surface of polysilicon film
119
.
Between adjacent trenches
101
h
, floating gate electrodes
122
are arranged on silicon substrate
101
with a gate insulator film
121
disposed therebetween. Floating gate electrodes
122
are composed of a bottom conductor film
122
a
and a top conductor film
122
b.
A silicon oxide film
123
is so laid as to be in contact with the side walls of lower conductor layer
122
a
and with gate insulator film
121
. On silicon oxide film
123
is a side-wall insulator layer
124
made of a silicon nitride film.
Adjacent floating gates
122
are isolated from each other by trenches
101
h
formed therebetween.
A control gate electrode
131
is formed on floating gate electrodes
122
with a dielectric film
125
disposed therebetween. Control gate electrode
131
is extended from the right to the left side of the drawing.
A method for fabricating the semiconductor device of
FIG. 11
will be described as follows.
FIGS. 12
to
15
show cross sectional views depicting a method for fabricating the semiconductor device of FIG.
11
. Referring to
FIG. 12
, gate insulator film
121
is formed on the surface of silicon substrate
101
. A polysilicon film, a silicon oxide film, and a silicon nitride film are formed on gate insulator film
121
in this order. A patterned resist pattern is provided on the silicon nitride film. Then, the silicon nitride film, the silicon oxide film, and the polysilicon film are etched in accordance with the resist pattern. As a result, a silicon nitride film
127
, a silicon oxide film
128
, and lower conductor layer
122
a
are completed. While using silicon nitride film
127
and lower conductor layer
122
a
as a mask, impurity ions are implanted into silicon substrate
101
, thereby forming impurity regions
116
as source and drain regions.
Referring to
FIG. 13
, silicon oxide film
123
and a silicon nitride film are accumulated on the surface of silicon substrate
101
, and the entire surface of silicon substrate
101
is etched back so as to form side-wall insulator layer
124
and silicon oxide film
123
. While using silicon nitride film
127
and side-wall insulator layer
124
as a mask, the entire surface of silicon substrate
101
is etched back so as to form trenches
101
h
. The surfaces of trenches
101
h
are oxidized to form an oxide layer
111
.
Referring to
FIG. 14
, silicon oxide film
112
is formed by CVD (chemical vapor deposition), and polysilicon film
119
is accumulated on silicon oxide film
112
. The entire surface of semiconductor substrate
1
is, etched back so as to expose silicon nitride film
127
.
Referring to
FIG. 15
, the surface of polysilicon film
119
is oxidized to form oxide layer
117
. Then, silicon nitride film
127
is eliminated.
Referring to
FIG. 11
, after the surface of lower conductor layer
122
a
is washed, a polysilicon film is formed. The polysilicon film is etched to form upper conductor layer
122
b
. On upper conductor layer
122
b
is formed dielectric film
125
made of an ONO (oxide nitride oxide) film composed of a silicon oxide film, a silicon nitride film, and another silicon oxide film. Control gate electrode
131
is arranged on dielectric film
125
, thereby completing the semiconductor device shown in FIG.
11
.
The problems of the aforementioned prior art semiconductor device will be described as follows with reference to the drawings.
FIG. 16
shows a cross sectional view depicting a problem of the prior art semiconductor device. Referring to
FIG. 16
, in a prior art process, silicon substrate
101
is exposed in an oxidizing atmosphere while oxide layer
117
is being formed. During the exposure, an oxygen gas permeates through silicon oxide film
112
and oxide layer
111
so as to reach silicon substrate
101
. Consequently, the portions of silicon substrate
101
that are in contact with surface
101
s
are oxidized to become oxide layer
135
. Oxide layer
135
, which is larger in volume than silicon, causes crystal defects in its vicinity. The occurrence of such crystal defects in the channel portions under floating gate electrodes
122
makes arsenic in impurity regions
116
be captured by the crystal defects, which shortens the substantial channel length. Supplying a potential difference across adjacent impurity regions in the transistors will cause a current to flow continuously due to the punch through between the source and the drain. This causes a problem that a selected memory cell transistor malfunctions, thereby deteriorating the reliability of the semiconductor device. There is a similar problem in forming oxide films of dielectric film
125
, which is an ONO film.
FIG. 17
is a cross sectional view depicting another problem of the prior art semiconductor device. Referring to
FIG. 17
, electrons usually travel in the direction indicated by an arrow
142
between the source and the drain. However, some of the electrons traveling from the source to the drain proceed in the direction indicated by an arrow
143
and are captured by the trap level in gate insulator film
121
, which is referred to as a hot electron phenomenon. The phenomenon causes the threshold voltage of the transistors to fluctuate, thereby decreasing the reliability of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention, which has been contrived to solve the aforementioned problems, has an object of providing a highly reliable semiconductor device.
The semiconductor device of the present invention includes a semiconductor substrate, a gate electrode, a side-wall insulator layer, and a nitrogen-containing layer. The semiconductor substrate includes a first surface and a second surface which is adjacent to the first surface and defines trenches. The gate electrode has side wall, and is formed on the first surface of the semiconductor substrate with a gate insulator film interposed therebetween. The side-wall insulator layer is formed on the side wall and on a portion of the first surface. The nitrogen-containing layer is so formed as to extend from the portion of the semiconductor substrate that is in the vicinity of second surface to the portion of the semiconductor substrate that is in the vicinity of the interface between the side-wall insulator layer and the semiconductor substrate. The nitrogen-containing layer has a higher concentration of nitrogen than the first surface of the semiconductor substrate under the gate electrode.
In the semiconductor device thus structured, the nitrogen-containing layer is so formed as to extend from the portion of the semiconductor substrate that is in the vicinity of the second surface defining the trench to the portion of the semiconductor substrate that is in the vicinity of the interface between the side-wall insulator layer and the semiconductor substrate. In this region, the presence
McDermott & Will & Emery
Renesas Technology Corp.
Soward Ida M.
Zarabian Amir
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