Field effect transistor with reverse dopant grandient region

Details Field effect transistor with reverse dopant grandient region Field effect transistor with reverse dopant grandient region

2002-12-10

2004-09-21

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06794722

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device, more particularly, a metal oxide semiconductor field-effect transistor (MOSFET) which operates at high frequency.
2. Background Art
FIG. 13
is a cross-sectional view showing the structure of a typical MOSFET. The MOSFET is formed on a lightly-doped p-type (p
−
-type) silicon substrate
1
. A lightly-doped n-type (n
−
-type) impurity layer
2
is formed on the substrate
1
in a region where a drain is to be formed. Further, a heavily-doped n-type (n
+
-type) impurity layer
3
is formed on the substrate
1
in a region where a source is to be formed and in another region where a drain is to be formed.
FIG. 14
is a view for describing the capacitance Cds of the drain region when a drain voltage is applied to the MOSFET. When a drain voltage Vds is applied to the MOSFET, a depletion layer is formed between a junction between the n
−
-type impurity layer
2
and the p
−
-type silicon substrate
1
, indicated as a hatched portion in the drawing. Since the depletion layer acts as a dielectric, a capacitance Cds arises in a junction between the n
−
-type impurity layer
2
and the p
−
-type silicon substrate
1
. As the drain voltage increases, the thickness of the depletion layer increases. Thus, in general, as the drain voltage increases, the capacitance Cds becomes smaller.
The capacitance of a drain region becomes a factor for decreasing the operating speed of the MOSFET. Hence, the capacitance must be minimized. In particular, in the case of the MOSFET which operates at high frequency, an interval Lgd (see
FIG. 13
) between the gate and the drain must be made comparatively longer in order to increase the withstand voltage characteristic. For this reason, the capacitance of a junction between a substrate and a drain region tends to increase. If the capacitance Cds increases, an output voltage leaks to the p
−
-type silicon substrate
1
and drops with an increase in operating frequency, thereby deteriorating power efficiency. In terms of an increase in operating speed and output efficiency, a reduction in the capacitance of the drain region is an important problem.
A relationship between the capacitance of a drain region in a high-frequency MOSFET and output power thereof is described in a paper edited by Maylay Trivedi et. al. entitled “Performance Modeling of RF Power MOSFETs” (IEEE Transactions on Electron Device, Vol. 45, No. 8, August 1999, pp. 1794 to 1801). In the paper, a relationship between power P
0
output from the MOSFET and parasitic capacitance C
oss
between the source and drain regions is expressed as Eq. (1) provided below; namely,
P
0
=V
IN
2
gm
2
R
L
/{2·(1+&ohgr;
2
C
oss
2
R
L
2
)}  (1)
where V
IN
is an input voltage, &ohgr; is mutual conductance; R
L
is a frequency; and R
L
is load resistance.
According to Eq. (1), P
0
becomes higher as the parasitic capacitance C
oss
becomes smaller.
The capacitance can be diminished by means of shortening the interval Lgd. However, as mentioned previously, the interval Lgd affects the withstand voltage characteristic of the MOSFET, and therefore shortening of the interval Lgd is not preferable. In other words, in relation to design of a high-frequency MOSFET, a tradeoff exists between an increase in a withstand voltage characteristic and an increase in the operating speed and output efficiency.
SUMMARY OF THE INVENTION
The invention aims at increasing an operating speed and output efficiency without involvement of a decrease in the withstand voltage characteristic of a high frequency MOSFET. To achieve the object, the present invention proposes two types of structures as the structure of a semiconductor device.
According to one embodiment of the present invention, a semiconductor device includes a semiconductor substrate of first conductivity type, an impurity region of second conductivity type which is formed as a source or drain of the semiconductor device in a surface of the semiconductor substrate and has a polarity opposite that of the semiconductor substrate, and an impurity region of first conductivity type formed below the impurity region of second conductivity type that is formed as the drain, so as to be joined to the impurity region of second conductivity type. The impurity region of first conductivity type is formed directly in the semiconductor substrate. Further, the quantity of impurity contained in the impurity region of first conductivity type increases with increasing distance from the junction of the impurity region of second conductivity type.
By means of such a structure, when a drain voltage is applied to the device, a depletion layer of a junction is rendered easy to spread, because doping profile in a depthwise direction is set such that a doping level increases gently.
According to another embodiment of the present invention, a semiconductor device includes a semiconductor substrate of first conductivity type, an impurity region of second conductivity type which is formed as a source or drain of a semiconductor device on the surface of the semiconductor substrate, and an oxide film layer formed below the impurity region of second conductivity type that is formed as the drain, so as to be joined to the impurity region of second conductivity type.
By means of such a structure, no p-n junction is present at a position located below the impurity region formed as a drain. Hence, the capacitance stemming from application of a drain voltage can be made small. Other and further objects, features and advantages of the invention will appear more fully from the following description.


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S. Wolf. Silicon Processing for the VLSI Era Vol.-1Process Technology. 1986. Lattice Press, pp. 295-297.*
Shindo, M., et al., “High Power LDMOS for Cellular Base Station Applications”, Proceeding of ISPSD 2001, pp. 107-110.
Trivedi, Malay, et al. “Performance Modeling of RF Power MOSFET's”, IEEE Transactions on Electron Devices, vol. 46, No. 8, Aug. 1999, pp. 1794-1801.

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