Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-02-01
2004-03-16
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
06708259
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to memory transfer engines in semiconductor chips.
BACKGROUND OF THE INVENTION
As the demand for faster microprocessors increases, there is a need for decreasing data processing latency. One of the ways this is done is by employing split read transactions, where reading data is split into two different actions—requesting a read and providing the requested data. The split transaction allows the processor to perform other tasks while the requested data is being fetched, thus reducing processing latency.
In a memory transfer engine having a plurality of memory transfer controllers (MTCs) for transferring data to memory, a processor may be shared among the various MTCs. If split read transactions are employed, the processor can request data for at least one MTC and perform at least one other task for another MTC while the requested data is fetched. Such an arrangement increases the data bandwidth of the system.
If the above arrangement is employed, it is necessary to have both a hardware context-switching system for switching the processor to another MTC and a notification system for waking up inactive MTCs in order for the system to operate efficiently. It is an object of this invention to provide a mechanism for waking up an idle MTC in response to notification of an event from an external source.
SUMMARY OF THE INVENTION
A semiconductor chip's memory transfer engine (MTE) consists of a plurality of memory transfer controllers (MTCs), each MTC having direct access to its associated plurality of dual port data memory (DPDM) registers and hardware registers. Each MTC can also access the DPDM registers and hardware registers associated with the other MTCs in the MTE.
The MTE has one hardware processor which is shared among the MTCs in a round-robin, time-sliced manner. When an executing MTC relinquishes control of the processor, an arbiter chooses the next MTC to control the processor from the MTCs that are ready to execute an instruction.
Two wake-up mechanisms are available to make an idle MTC ready to execute in response to a wake-up event from an external source, thus facilitating event-driven multithreading of the MTCs in an MTE.
The first mechanism, Parameter List Pointer (PLP) FIFO wakeup, wakes up an MTC after an external agent writes to an MTC's PLP FIFO. This activates the MTC's run bit, placing the MTC in a state where it can execute instructions. This mechanism allows the MTC to distinguish between multiple possible originators of multiple possible wake-up events. Wake-up events may be queued. Events may be directed to particular MTCs or to the next MTC available to process the event.
The second mechanism wakes up an MTC after an external agent writes to an MTC's external wake-up address. This activates the MTC's run bit. This approach only recognizes one event and one source. Events may not be queued using this approach.
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Cradle Technologies, Inc.
Schneck Thomas
Strottman Nissa
Verbrugge Kevin
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