Encoding method and memory device

Details Encoding method and memory device Encoding method and memory device

1999-11-23

2004-05-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S756000, C714S763000

Reexamination Certificate

active

06732322

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an encoding method and a memory apparatus applicable preferably to a multi-valued recording flash memory, a memory card using that flash memory and so on.
BACKGROUND ART
In recent years, as the memory apparatus, semiconductor memories such as flash memories have been widely used. In the flash memory, data are recorded by using cell arrays that comprise a large number of memory cells (numbering usually about 65 million) comprising floating gates (charge storage layer) and control gates arranged in layered fashion on a semiconductor substrate (see FIG.
16
). In this case, each of the cell arrays retains data as charge quantities stored in floating gates.
FIGS. 17A and 17B
illustrate a structure of a memory cell
100
used in a flash memory. That is, the memory cell
100
is so formed as to stack a charge storage layer (floating gate)
102
and a control gate
103
on a semiconductor substrate
101
. When a data item is to be written to the memory cell
100
, the quantity of charge held in the floating gate
102
is controlled so that it is reached to one of two threshold voltages shown in
FIG. 18
according to the data (“0” or “1”) to be recorded. On the other hand, when the data item is to be read from the memory cell
100
, by using a reference voltage set between the two threshold voltages, it is determined that the data item in the memory cell
100
is judged to be “0” or “1” depending on whether the threshold voltage of the memory cell
100
is higher or lower than the reference voltage.
It is critical to semiconductor memories to prevent declines in reliability stemming from diverse effects of high-integration, high-density circuit implementation. As part of the effort to preserve memory device reliability, an error correcting circuit based on an error correcting code such as the Hamming code is often incorporated in the semiconductor memory in order to counter aging-induced failures such as faulty cells, resulting in particular from an increasing number of write and erase operations.
The error correcting code is a redundant code called check data attached to information data and then the check data are used to correct an error in the entire code. For example, 10-bit check data as shown in
FIG. 19
are added to an abbreviated Hamming code for a 512-bit block of information data so that, even if one error occurs in the 522-bit code, the error may be corrected.
FIG. 20
shows a structure of a flash memory
110
incorporating an error correcting circuit based on the Hamming code therein. The flash memory
110
comprises cell arrays
111
having a plurality of memory cells, an encoder
112
converting input data Din into an abbreviated Hamming code to provide write data WD to be written to the cell arrays
111
and a Hamming code decoder
113
providing output data Dout by subjecting read data RD retrieved from the cell arrays
111
to an error correction process. In this case, the encoder
112
and Hamming code decoder
113
constitute an error correcting circuit. The encoder
112
adds 10-bit check data to every 512-bit block of input data Din and the abbreviated Hamming code for the 512-bit information data is created.
In the flash memory
110
shown in
FIG. 20
, a data write operation takes place as follows. That is, input data Din are first inputted to the encoder
112
. Then, the encoder
112
converts the input data Din into the abbreviated Hamming code for 512-bit information data, thereby generating write data WD. The write data WD outputted from the encoder
112
are fed and written to the cell arrays
111
.
On the other hand, a data read operation is carried out as follows. Read data RD retrieved from the cell arrays
111
are inputted to the Hamming code decoder
113
. If one code of the read data RD contains no error, the Hamming code decoder
113
outputs the information data unchanged as output data Dout. If one code of the read data RD has one erroneous bit, the Hamming code decoder
113
outputs the information data as the output data Dout after correcting the error.
Next, an example in which an abbreviated BCH code (Bose-Chaudhuri-Hocquenghem code) is used as an error correcting code capable of correcting two errors in one code will be described. The BCH code and techniques of code abbreviation are discussed illustratively by Hideki Imai in “Code Theories” (Institute of Electronics, Information and Communication Engineers of Japan) among others. For example, 20-bit check data are added to the abbreviated BCH code for 512-bit information data as shown in
FIG. 21
, thereby enabling to correct two errors in the 532-bit code.
FIG. 22
shows a structure of a flash memory
120
incorporating an error correcting circuit based on the BCH code. The flash memory
120
comprises cell arrays
121
having a plurality of memory cells, an encoder
122
for converting input data Din into an abbreviated BCH code to provide write data WD to be written to the cell arrays
121
and a BCH code decoder
123
for subjecting read data RD retrieved from the cell arrays
121
to an error correction process to provide output data Dout. In this case, the encoder
122
and the BCH code decoder
123
constitute an error correcting circuit. The encoder
122
adds 20-bit check data to every 512-bit block of input data Din and the abbreviated BCH code capable of correcting two errors regarding the 512-bit information data is created.
In the flash memory
120
shown in
FIG. 22
, a data write operation takes place as follows. That is, input data Din are first inputted to the encoder
122
. Then, the encoder
122
converts the input data Din into the abbreviated BCH code for 512-bit information data, thereby generating write data WD. The write data WD outputted from the encoder
122
are fed and written to the cell arrays
121
.
On the other hand, a data read operation is carried out as follows. Read data RD retrieved from the cell arrays
121
is inputted to the BCH code decoder
123
. If one code of the read data RD contains no error, the BCH code decoder
123
outputs the information data unchanged as output data Dout. If one code of the read data RD has one or two erroneous bits, the information data are outputted as the output data Dout after correcting the error.
As shown in
FIGS. 20 and 22
, the error correcting circuit incorporated in the flash memory
110
or
120
can suppress errors of written data despite a certain number of faulty cells caused by aging. However, generally in the error correcting code, a relatively large quantity of the check data, which are redundant check data, are required to correct a fairly large number of errors and thus, the number of memory cells to be used is increased as well as the scale of the error correcting circuit to be incorporated is enlarged.
Next, a memory card constituted by a plurality of flash memories (flash memory chips) will be described. As a memory device for storing quantities of data that cannot be handled by a single-chip flash memory, the memory card includes multiple flash memories and a controller.
FIG. 23
shows a structure of a memory card
130
with a controller having an error correcting circuit based on the BCH code. The memory card
130
includes two flash memories
131
and
132
and a controller
133
for writing and reading data to and from these flash memories
131
and
132
.
The controller
133
comprises a card interface
134
for exchanging data with an entity outside the card, an encoder
135
for converting input data Din into an abbreviated BCH code to provide write data WD to be written to the flash memories
131
and
132
, a BCH code decoder
136
for subjecting read data RD from the flash memories
131
and
132
to an error correction process to provide output data Dout, and a flash interface
137
for controlling the writing and reading of data to and from the flash memories
131
and
132
.
In the above structure, the encoder
135
and the BCH code decoder
136
constitute an error correcting circuit. The encoder
135
adds 20-bit check data to every 5

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