Dynamic random access memory including a logic circuit and...

Details Dynamic random access memory including a logic circuit and... Dynamic random access memory including a logic circuit and...

2002-08-30

2004-03-02

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S298000, C257S308000, C257S309000, C257S305000, C257S516000, C257S532000, C257S303000

Reexamination Certificate

active

06700152

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device provided with a dynamic random access memory (DRAM) and a process for manufacturing it, and, more particularly, to a semiconductor integrated circuit suitably applied in case it is constituted by a large scale integrated circuit (LSI) and a method of manufacturing it.
BACKGROUND ART
The integration of DRAMs into semiconductor integrated circuits has become is remarkably developed. In particular, the integrated circuits provided with high functions in which the DRAM includes a logical circuit have been realized. DRAM is composed of plural memory cells arrayed in a matrix composed of rows and columns on a semiconductor substrate. The memory cell is composed of a storage capacitor for storing information and a MOS field effect transistor (hereinafter called a MOS transistor) for controlling the input/output of an electric charge to/from the capacitor.
The capacitor is provided with a structure in which a dielectric film is held between two electrode films, and the MOS transistor is composed of a gate electrode and two diffusion layers (a drain area and a source area). One electrode film of the capacitor is connected to one diffusion layer of the MOS transistor, and the other electrode film of the capacitor is connected to a constant-voltage power source. The on and off states of the MOS transistor are controlled by voltage applied to the gate electrode. When the electric charge is supplied from the other diffusion layer to the capacitor in the on state, writing is executed, and in the other on state, the electric charge stored in the capacitor is extracted from the other diffusion layer.
DRAM is composed of plural memory cells, and one of which
15
is constituted so that the gate electrodes in each row are connected via an individual word line, and the other diffusion layers in each column are connected via an individual bit line. A peripheral circuit for controlling memory cells in DRAM is provided. Wiring between the memory cells and the peripheral circuit, in addition to the word line, the bit lines, and internal wiring in the memory cells, are formed by a metal wiring layer. As the capacity of DRAM is increased, the number of the wiring layers is increased. The capacitor is formed inside the intermediate layers of such plural wiring layers.
As the degree of integration becomes higher to increase the memory capacity of DRAM, the size of each part becomes smaller and the projective area (the area viewed from the top of the integrated circuit) of the capacitor decreases. In the meantime, as for the capacitor, since the capacitance to some extent is required to be secured, the substantial area of the capacitor can be increased, in addition to using a material high in a dielectric constant and thinning the dielectric layer. As the former two have a limit, various devices are made so that the substantial area is increased without increasing the projective area. To increase the area, the capacitor is often formed utilizing the height by increasing the thickness of the wiring layer in which the capacitor is arranged. A multilayer type and others can be given in addition to the crown structure (cylindrical structure) and the fin structure, as an example.
However, as the thickness of the capacitor layer in which the capacitor is formed is increased, it cannot be avoided that a difference in level is created between the memory cell portion and the peripheral circuit without the capacitor. (For example, see pages 42 to 44 in “Nikkei Microdevice” No. 117, published in March, 1995 by Nikkei BP, Japan.)
FIG. 24
shows a general example of a structure with a difference in the level. In the example, MOS transistors
6
which respectively function as a memory cell and a transistor
7
which functions as a peripheral circuit are formed. A bit line layer
12
and three wiring layers
18
,
24
and
32
are formed on a passivated insulating film layer
8
in which the gate electrodes
3
of both are formed The capacitor is formed in a first wiring layer
18
in a crown structure. The capacitor is formed so that a dielectric film
28
is held between a lower metal film
27
(hereinafter called a storage node (SN)) and an upper metal film
34
(hereinafter called a plate electrode (PL)), as shown in an enlarged drawing in the lower part of FIG.
24
. The storage node
27
is connected to the diffusion layer
4
of the MOS transistor
6
via a contact plug
9
, a plug
14
and a pad
10
, and the plate electrode
34
is connected to a wire
62
for supplying constant voltage in a third wiring layer
32
via plugs and a pad in the first and second wiring layers
18
and
24
.
In the above example of the conventional type, as the capacitor is required to be in a crown structure of high level, there is a difference in the level between the memory cell area and the peripheral circuit area. When the difference in the level exceeds a certain degree, there is the problem that, in lithographic processing afterward, it is difficult to form a wiring pattern in a predetermined shape. The cause is the depth of the focus of an exposure apparatus. If the difference in the level exceeds the allowable range of the depth of the focus, the focus is off in a part with the difference in the level, luminous energy decreases, exposure is short, and a predetermined shape is not formed Particularly, when the difference in the level exceeds 1 &mgr;m, the problem is remarkable.
To solve the above problem, a method of forming a sacrificed film overall and reducing the quantity of the difference in the level by etching or polishing the film may be adopted. However, in that case, the number of processes is increased. If a connecting hole is formed, both an area in which etching is excessive and an area in which etching is short are created, because the depth of the connecting hole up to a metal film is different in the part with the difference in levels. Particularly in the part in which the hole is deep, the shortage of etching and the failure of the conduction of the wire is caused by the filling shortage of conductive material. Therefore, the problem of the difference in the level occurs in the semiconductor integrated circuit including DRAM and the logical circuit.
A method of forming a capacitor on a wiring layer to reduce the difference in the level due to a capacitor as disclosed in Japanese Patent Laid-open (Kokai) No. Hei6-125059 is proposed. In this method, a connecting hole extending through a wiring layer and a bit line layer is formed by etching to connect the storage node of the capacitor formed on the wiring to a diffusion layer. Afterward, the storage node and the diffusion layer are connected by embedding polysilicon in the connecting hole The hole which is 2 &mgr;m or more in depth, with the aspect ratio of 8 or more is formed by dry etching. However, only a hole which is 2 &mgr;m or less in depth, with the aspect ratio of 4 or less, can be etched with a high yield and reproductivity by the current dry etching technique Therefore, there is a problem that the capacitor cannot be formed on the wiring.
As the manufacturing process of the peripheral, circuit is not considered, there is also the problem that the number of processes is increased, for example, because the formation of the connecting hole and a contact plug for connecting the storage node and the diffusion layer is independent from the formation of the connecting hole and the plug in the peripheral circuit portion.
Further, as a polysilicon plug is formed after the wiring is formed, the temperature of 500° C. or more which is polysilicon forming temperature, is applied to the wiring and the aluminum is deformed and decomposed if aluminum is used as the wiring material.
As described above, the structure of the capacitor is complicated because of fining, the number of processes is increased, and the above complication is the main cause of the increased manufacturing cost In addition, since the capacitor, the wiring of the peripheral circuit, and the wiri

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