Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-19
2004-01-20
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C365S145000, C365S149000, C361S313000
Reexamination Certificate
active
06680499
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-352265, filed Nov. 20, 2000; and No. 2001-341392, filed Nov. 7, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a ferroelectric capacitor, particularly, to a semiconductor device having a highly integrated ferroelectric memory cell and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a ferroelectric memory cell is being developed as a non-volatile semiconductor memory device having a low power consumption and a high reliability. For example, a conventional ferroelectric memory device using a ferroelectric capacitor comprising a PZT (PbZr
1−x
TiO
x
) film is constructed as shown in FIG.
1
.
As shown in the drawing, diffusion layers
101
to
103
are formed in a semiconductor substrate
100
, and gates
104
to
107
are formed on the semiconductor substrate
100
adjacent to these diffusion layers
101
to
103
. A plug
108
for connecting the diffusion layer
101
to a lower electrode
111
of a ferroelectric capacitor is formed on the diffusion layer
101
. Likewise, a plug
109
for connecting the diffusion layer
102
to a wiring
121
is formed on the diffusion layer
102
. Further, a plug
110
for connecting the diffusion layer
103
to a lower electrode
117
of a ferroelectric capacitor is formed on the diffusion layer
103
.
The lower electrode
111
common to two adjacent ferroelectric capacitors is formed above the gate
104
, the diffusion layer
101
and the gate
105
. One ferroelectric capacitor including a ferroelectric film
112
and an upper electrode
113
and another ferroelectric capacitor including a ferroelectric film
114
and an upper electrode
115
are formed on the lower electrode
111
. The ferroelectric capacitor including the ferroelectric film
112
and the upper electrode
113
is positioned above the gate
104
. On the other hand, the ferroelectric capacitor including the ferroelectric film
114
and the upper electrode
115
is positioned above the gate
105
.
Similarly, a lower electrode
117
common to two adjacent ferroelectric capacitors is formed above the gate
106
, the diffusion layer
103
and the gate
107
. One ferroelectric capacitor including a ferroelectric film
118
and an upper electrode
119
and another ferroelectric capacitor including a ferroelectric film
122
and an upper electrode
123
are formed on the lower electrode
117
. The ferroelectric capacitor including the ferroelectric film
118
and the upper electrode
119
is positioned above the gate
106
. On the other hand, the ferroelectric capacitor including the ferroelectric film
122
and the upper electrode
123
is positioned above the gate
107
.
The upper electrode
115
and the upper electrode
119
are connected to the wiring
121
via plugs
116
and
120
, respectively. Further, the wiring
121
is connected to the diffusion layer
102
through a plug
109
.
As described above, in the conventional semiconductor memory device comprising ferroelectric capacitors, a ferroelectric capacitor comprising a ferroelectric film formed between a pair of the upper electrode and the lower electrode is formed on the memory cell transistor in a 1:1 relationship. Incidentally, in the semiconductor memory device comprising a ferroelectric capacitor, the similar structure is repeated in the left-right direction in
FIG. 1
, through the repeated structure is not shown in FIG.
1
.
In the prior art shown in
FIG. 1
, a plurality of unit cells each comprising a single ferroelectric capacitor connected in parallel to a single memory cell transistor are connected in series. The particular construction is described in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-255483 as a ladder-type ferroelectric memory.
The conventional ladder-type ferroelectric memory disclosed in the literature quoted above attracts attentions in that a ferroelectric memory comprising a plurality of unit cells that are connected in series, each unit cell being constructed such that both ends of a capacitor (C) are connected between the source and drain of a memory cell transistor (T), said ferroelectric memory being hereinafter referred to as the “series connected TC-parallel unit ferroelectric memory”, is adapted for achieving a high degree of integration.
In the conventional ferroelectric capacitor, however, it is possible for the damage in the manufacturing process to produce a prominent influence with reduction in the capacitor size so as to deteriorate the capacitor characteristics. Particularly, in forming a capacitor by utilizing a reactive ion etching (RIE), it is necessary to ensure an alignment margin in view of the possibility of the over-etching of the side surface of the capacitor and in view of the deviation in the alignment of the mask. As a result, the shape of the capacitor obtained after the etching is rendered smaller than the design value, leading to the possibility that it is impossible to obtain a required capacitance.
It should also be noted that, since the ferroelectric film of the ferroelectric capacitor is formed of a single layer, the processing of the capacitor is rendered difficult and the capacitor tends to incur the damage on the process, if the size of the ferroelectric capacitor is reduced in accordance with reduction in the chip size of the semiconductor memory device. As a result, a problem is generated that the electrical characteristics, the reliability and the manufacturing yield of the semiconductor memory device are adversely affected. The present invention, which has been achieved in an attempt to overcome the above-noted problems, is intended to provide a semiconductor memory device that permits enhancing the degree of integration without decreasing the capacitance of the memory cell capacitor and to provide a method of manufacturing the particular semiconductor memory device.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film.
According to another aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate, a first transistor formed on the semiconductor substrate and having a gate, a source formed of a first diffusion layer and a drain formed of a second diffusion layer, the first and second diffusion layers being arranged to face each other with the gate interposed therebetween, a second transistor formed on the semiconductor substrate, positioned adjacent to the first transistor, and having a gate, a source formed of a third diffusion layer and a drain formed of a fourth diffusion layer, the third and fourth diffusion layers being arranged to face each other with the gate interposed therebetween, a first plug electrode connected to the first diffusion layer, a second plug electrode connected to the second diffusion layer, a third plug electrode connected to the third diffusion layer, a fourth plug electrode connected to the fourth diffusion layer, a first bit line connected to the second plug electrode, a second bit line connected to the fourth plug electrode, a first electrode connected to the first diffusion layer through the first plug electrode, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, a third electrode formed on the second ferroe
Kanaya Hiroyuki
Kumura Yoshinori
Kunishima Iwao
Kabushiki Kaisha Toshiba
Nelms David
Tran Mai-Huong
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