Methods and apparatus for substantially memory-less coherence tr

Details Methods and apparatus for substantially memory-less coherence tr Methods and apparatus for substantially memory-less coherence tr

1996-07-01

1999-08-17

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711141, 711144, 711145, 39520043, 39520046, G06F 1336, G06F 1342

Patent

active

059408600

ABSTRACT:
An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus. There is further included a protocol transformer logic coupled to the receiver logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device irrespective of the external device speed or protoco.

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