Method of designing active region pattern with shift dummy...

Details Method of designing active region pattern with shift dummy... Method of designing active region pattern with shift dummy...

2002-10-30

2004-10-26

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S015000, C326S047000, C326S101000

Reexamination Certificate

active

06810511

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of designing an active region pattern with a shift dummy pattern, and more particularly, to a method adding a shift dummy pattern into an diffusion region for the process of forming a shallow trench isolation. Therefore, a better planarization effect is obtained in the subsequent process of chemical mechanical polishing (CMP), and a circuit problem induced by various parasitic capacitors is resolved.
2. Description of the Related Art
As the design of an integrated circuit is more and more complex, the line width of fabrication process reduced narrower than 1 &mgr;m causes a restriction the development of a trench isolation technique in a complementary metal-oxide-semiconductor (CMOS) is thus restricted. While performing chemical mechanical polishing for planarization, if a under layer has a pattern on which the distance between devices is over 10 &mgr;m, a dishing recess is formed on the region without a device thereon after polishing. Thus, a global planarization is affected. This is called as a dishing effect. In
FIG. 1A
to
FIG. 1D
, a shallow trench isolation formed by a conventional technique of chemical mechanical polishing is shown.
In
FIG. 1A
, on a semiconductor substrate
10
, for example, a silicon substrate, a pad oxide layer
11
and a dielectric layer
12
, for example, a silicon nitride layer are formed in sequence. Using photolithography and etching, a device region
13
is formed on the substrate
10
. Using a photo-resist layer (not shown) on the device region
13
as a mask, the substrate
10
is etched, for example, by anisotropic etching, to form several trenches with certain depths. In
FIG. 1B
, using chemical vapor deposition (CVD), an oxide layer
14
is formed over the substrate
10
. The oxide layer
14
is polished by chemical mechanical polishing with the dielectric layer
12
as a stop layer, so that several trench isolations
15
,
16
are formed as shown in FIG.
1
C.
After the formation of trench isolations
15
,
16
, subsequent processes, for example, removing the pad oxide layer
11
and the dielectric layer, forming a gate oxide layer
17
and a poly-silicon layer
18
, is performed as shown in FIG.
1
D. As shown in the figure, the width of each trench isolation is not identical. For example, the region of trench isolation
16
is larger than the region of the trench isolation
15
. The polysilicon layer
18
is well planarized on the trench isolation
15
. On the contrary, the poly-silicon layer
18
on the trench isolation
15
has a smooth recess. Thus, using chemical mechanical polishing, only a local planarization is achieved. The global planarization cannot be achieved.
To resolve the drawback mentioned above, conventionally, a dummy pattern is added to the active region pattern to improve the uniformity of chemical mechanical polishing. However, a parasitic capacitance is induced by doing so to affect the performance of devices. The metal line on different dummy pattern causes a time delay by different parasitic capacitance, and therefore, causes a circuit problem. In
FIG. 2
, a conventional method of designing an active region pattern with a dummy pattern is shown. Metal lines
20
,
22
are formed on different locations of the dummy pattern
24
, and the dummy pattern
24
comprises columns
24
a
to
24
d
. For example, the metal line
20
is formed on a column
24
c
of the dummy pattern, and the metal line
22
covers a part of the column
24
a
and a part of the column
24
b
of the dummy pattern
24
. Between the metal line
22
and the dummy pattern
24
, different parasitic capacitance is induced in practical application, so that a problem of different time order, for example, an RC delay is caused.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of designing an active region pattern with a dummy pattern. By shifting a predetermined dummy pattern, the parasitic capacitance between each metal line and the dummy pattern is identical. Therefore, an identical RC time is obtained.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of designing an active region pattern with a dummy pattern. An integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5278105 (1994-01-01), Eden et al.
patent: 5341049 (1994-08-01), Shimizu et al.
patent: 5438281 (1995-08-01), Takahashi et al.
patent: 6311147 (2001-10-01), Tuan et al.
patent: 63025883 (1988-02-01), None
patent: 01138681 (1989-05-01), None
patent: 03117113 (1991-05-01), None
patent: 03207079 (1991-09-01), None
patent: 09321595 (1997-12-01), None
Kim et al., “An isolated-open pattern to de-embled pad parasitics [CMOSFETs]”, IEEE Microwave and Guided Wave Letters, Vo 8, No. 2, Feb. 1998, pp. 96-98.

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