Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-12-14
2004-05-11
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189011, C365S233500
Reexamination Certificate
active
06735139
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor memory devices that must be periodically refreshed, such as dynamic random access memory (“DRAM”) devices. More particularly, the present invention relates to a system and method which provides asynchronous static random access memory (“SRAM”) functionality with a DRAM array by selectively interrupting external memory commands, such as read and write commands, to perform internal refresh operations.
BACKGROUND OF THE INVENTION
An SRAM is one type of semiconductor memory device that typically utilizes several transistors within each memory cell of the device to store electronic data. The static storage mechanism of an SRAM has the benefit of not requiring any refresh cycles to maintain stored data. However, the relatively large number of transistors required to form the memory cells within SRAM devices undesirably increase the cost and size of these semiconductor memory devices relative to other types of devices.
A DRAM is another type of semiconductor memory device, which typically utilizes a single transistor and a capacitor within each memory cell of the device to store electronic data. Unlike an SPAM device, a DRAM device requires periodic refreshing in order to maintain stored data. While DRAM devices typically have a reduced cost and increased memory density relative to SRAM devices, DRAM devices require refresh cycles to retain data.
Many systems are adapted to operate with only DRAM devices or with only SRAM devices, such as asynchronous SRAM devices. In a system adapted to operate with an asynchronous SRAM device, memory arrays are accessed by detecting an external address change and then activating a memory controller, since an asynchronous SRAM device has no external clock input. The maximum setup time from the external address change to a write enable active state, as well as the duration of the write enable active pulse, are not defined in an asynchronous SRAM device. The write data is valid within the setup time and until the write enable state is deactivated. Furthermore, in these devices, a read command can change to a write command at any time and the write command may be indefinite in length.
FIG. 1
illustrates one example of a timing diagram
10
for a write cycle of a widely-used asynchronous SRAM device of the prior art. Timing diagram
10
includes signal values for the device's address lines (“ADDRESSES”), write enable (“WE#”), chip enable inputs (“CE
1
#”, “CE
2
”), upper and lower bit select inputs (“UB#”, “LB#”), and data lines (“DQ
15
-
8
”, “DQ
7
-
0
”). As shown in
FIG. 1
, before the external write enable signal WE# assumes a “low” value (i.e., a logic zero value), the system interprets the “high” value (i.e., a logic one value) of the signal as the read cycle and outputs the data on the data lines DQ
15
-
9
, DQ
7
-
0
. As a result, if a DRAM device were used in a system adapted to operate with this type of SRAM device, a refresh request could not be executed even after the read operation is finished. The address setup time T
AS
may have a minimum value of 0 nanoseconds (“ns”) and an undefined maximum value. The write pulse width T
WP
also has an undefined maximum value. Hence, the total length of the write cycle T
WC
(i.e., from the beginning of the setup time T
AS
to the end of the write recovery time T
WR
) can be very long and the write data can never be defined as valid before the write cycle finishes.
The foregoing attributes of an asynchronous SRAM device, would prevent a DRAM device from being refreshed if it were used within a prior system adapted to operate with asynchronous SRAM devices. As a result, a conventional DRAM array is not compatible with these prior systems. Some efforts have been made to limit maximum length of the parameters T
AS
, T
WP
and T
WC
in order to implement DRAM arrays within these prior systems. However, these efforts typically require an external device to monitor the timing and refresh operations of the system, thereby undesirably increasing the cost and complexity of the systems. Moreover, these prior art attempts to implement DRAM arrays within these systems do not provide asynchronous SRAM functionality. For example, these prior art systems prevent access to the memory from being requested while refresh operations are running.
It is therefore desirable to provide a memory system which overcomes the foregoing drawbacks of prior memory systems and which has the ability to provide asynchronous SRAM functionality with a DRAM array by interrupting the external memory commands, such as read and write commands, in order to execute refresh operations.
SUMMARY OF THE INVENTION
A first non-limiting advantage of the invention is that it provides a system which utilizes a DRAM array to provide asynchronous SRAM functionality.
A second non-limiting advantage of the invention is that it provides asynchronous SRAM functionality with a DRAM array by selectively interrupting external memory commands, such as read and write commands, to perform internal refresh operations.
A third non-limiting advantage of the invention is that it provides a self-contained DRAM array that can be used to replace an asynchronous SRAM device within a computer system without any additional control or devices, thereby decreasing the cost and increasing the memory density of the system.
According to a first aspect of the present invention, a memory system having asynchronous SRAM functionality is provided. The system includes: a DRAM array; a first portion adapted to receive external memory commands and to detect external address transitions in order to perform read and write operations on the DRAM array asynchronously; and a second portion adapted to selectively interrupt the external memory commands in order to perform refresh operations on the DRAM array.
According to a second aspect of the present invention, a DRAM apparatus having asynchronous SRAM functionality is provided. The apparatus includes a DRAM array; a first portion which is adapted to receive external memory commands, including external memory addresses for performing read and write operations on the DRAM array asychronously; a second portion which is adapted to periodically generate interrupt signals for refreshing the DRAM array; a third portion which is adapted to receive data for write operations on the array; and a fourth portion which is adapted to control the read and write operations performed on the DRAM array, and to interrupt the external memory commands to perform refresh operations the DRAM memory array in response to the generated interrupt signals.
According to a third aspect of the present invention, a method for providing asynchronous SRAM functionality with a DRAM array is provided. The method includes the steps of receiving external memory commands; detecting an external address transition in order to perform read and write operations on the DRAM array asynchronously; and selectively interrupting the external memory commands to perform internal refresh operations on the DRAM array.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.
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Alberti David L.
Auduong Gene
Gray Cary Ware & Freidenrich LLP
Silicon Storage Technology, Inc.
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