Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2001-02-13
2004-07-20
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S503000, C713S400000, C713S600000, C710S056000, C710S071000, C710S305000, C370S464000, C327S158000, C327S295000, C327S565000
Reexamination Certificate
active
06766464
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a deskew mechanism and more particularly, a link receiving a plurality of signals at a same incoming clock rate subject to skew among the signals.
BACKGROUND ART
In computer networks, data is generally sent and received in data packets. Different networks have different size interfaces to facilitate data transfer to other nodes and other networks. These interfaces may include multiple parallel lanes for sending and receiving data packets. Some modes of communication over such interfaces use only one lane for transferring data packets. These interfaces have the lowest link bit rate of ×1 (times one) the data rate over a lane. Another mode uses four parallel lanes to provide a link bit rate of ×4 the data rate over a lane. Thus, for a data rate of 2.5 Gb/sec, data can be provided in the ×4 mode at 10 Gb/sec. Still other modes use twelve parallel lanes for transferring data packets to provide a link bit rate referred to as a ×12 link.
Data packets being transported over cables or otherwise between networks having a number of parallel lanes are subject to skew and clock intolerance. “Skew” generally occurs when parallel bits reach an interface, or communication link, at different times because of differing transmission delays over each given lane. As data packets are received, clock intolerance arises when the incoming clock rate differs from the clock rate of the receiving apparatus.
In the prior art, buffers have been commonly used as intermediate storage areas that compensate for differences in rates in data flow when information is received by one computer device from another. In system area networks, for example, elastic buffers are often used to compensate for clock differences. An elastic buffer is a first in first out (“FIFO”) buffer that receives data at a variable input rate and outputs data at a variable output rate. In an elastic buffer, data can be inserted or removed at intervals identified by sequence signals in the data in a controlled manner to compensate for under runs or over runs of data resulting from the difference between the input rate and the output rate. Elastic buffers are typically used in each of a number of lanes.
Receive link logic manages all skip, training, and idle sequences in the data stream through the deskew queues and the elastic buffers. Skip sequences signal places along the data where a data packet may be omitted. Idle sequences indicate when there is no other data packet to transmit. Training sequences are identifiable sequences used to measure skew between the data lanes so that programmable delays may be determined and inserted to remove skew. If the receive link logic becomes overburdened by its tasks, there may be delays or errors in the data flow. Further, the elastic buffers may themselves cause skew when a skip sequence is lost or missed, such that retraining of the deskew function may be necessary.
SUMMARY OF THE INVENTION
An apparatus for compensating skew across a plurality of data interfaces includes a deskew buffer for each data interface. Data on each of the data interfaces arrives at a same incoming rate but in accordance with its own individual clock signal. A recovered clock signal is drawn from the clock signal of one of the data interfaces and coupled to all of the deskew buffers such that the data from all the data buffers is deskewed and output in accordance with the recovered clock signal. The apparatus may also include a link logic device that has a clock input connected to receive the recovered clock signal. A buffer interface may also be included to receive data from the link logic device in accordance with the recovered clock signal. The buffer interface may be a plurality of virtual lane buffers.
A method for compensating skew across a plurality of data interfaces includes writing data from each of the plurality of data interfaces into each of a plurality of deskew buffers in accordance with a clock signal from the respective data interface. Data is deskewed and read from the deskew buffers using a clock signal recovered from one of the plurality of data interfaces. The method may also include writing the data to a logic device using the recovered clock signal. Alternatively, the data may be written into an elastic buffer from the deskew buffers and then read at a local rate into the logic device.
Other objects and advantages of the invention will become apparent during the following description of the presently preferred embodiments of the invention taken in conjunction with the drawings.
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Lee Thomas
Park Vaughan & Fleming LLP
Patel Nitin C.
Sun Microsystems Inc.
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