PCB design and method for providing vented blind vias

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S115000, C438S613000, C438S614000, C029S852000

Reexamination Certificate

active

06787443

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to printed circuit boards (PCBs) and, more specifically, the present invention relates to a method an apparatus for a vented blind via in pad structure of a printed circuit board.
2. Background Information
A PCB typically includes a number of insulation and metal layers selectively patterned to provide metal interconnect lines (referred to herein as “traces”), and a plurality of electronic components mounted on one or more surfaces of the PCB and functionally interconnected through the traces. The routing traces typically carry signals that are transmitted between the electronic components mounted on the PCB. Some PCBs have multiple layers of routing traces to accommodate all of the interconnections.
Traces located within different layers are typically connected electrically by vias formed in the board. A via can be made by making a hole through some or all layers of a PCB and then coating or plating the interior hole surface with an electrically conductive material. A via that connects all layers of the PCB, including the outer layers, is called a “through via.” A via that connects one or more inner layers to an outer layer is a “blind via.”
In order to fabricate PCBs in which electrical components are mounted in higher densities, a via in pad structure is often used.
FIG. 1A
is a perspective view diagram illustrating a prior art blind via in pad. A blind via
12
is configured in pad
10
. The pad is formed on a multilayer PCB
16
. Blind via
12
has an opening at pad
10
and extends into PCB
16
. The walls of the blind via
12
are an electrically conductive material, such as copper. A solder mask (not shown) surrounds the pad
10
.
One of the conventional ways of mounting electrical components on a PCB is called surface mount technology (SMT). SMT components have terminations or leads (generally referred to as “contacts”) that are soldered directly to the surface of the PCB. The solder joint forms the physical and electrical connection between the component and the PCB. One conventional type of SMT component utilizes a ball grid array (BGA) to connect to the PCB. A BGA component has a plurality of solder balls on one surface, each of which represents an electrical contact.
The electrical contacts of an SMT component, such as a BGA component, are coupled to corresponding metallized mounting or bonding pads (also referred to as “lands”) on the surface of the PCB. Ordinarily one pad is dedicated to one SMT electrical contact.
Prior to mounting the SMT component on a PCB, the PCB is selectively coated with solder paste, using a mask (also referred to in the art as a stencil) that permits solder paste to coat just the pads. To mount an SMT component to a PCB, the component is carefully positioned or “registered” over the PCB so that its electrical contacts are aligned with the corresponding pads. Finally, the entire package is heated to a temperature that melts the solder paste (e.g., reflow soldering), to form a solder joint that is an electrical and physical connection.
During the heating process, one or more gas pockets can form within the soldier joint. Such gas pockets can be formed by expanding air bubbles trapped within the solder paste and/or blind via (also referred to as “outgassing”).
FIG. 1B
is a cross-sectional view diagram illustrating a prior art blind via in pad structure coupled to an electrical component. Blind via
12
is configured in pad
10
. The blind via
12
extends into multilayer PCB
16
and is electrically coupled to an inner conductive layer
14
. During the heating process to affix contact
20
of electrical component
22
to pad
10
by way of solder joint
24
, a gas pocket
26
was formed by trapped air within the blind via
12
. A solder mask (not shown) surrounds the pad
10
.
Such a gas pocket can cause the solder joint to expand to the point where it touches an adjacent solder joint and, thus, create a short circuit. In the case of BGA components, this phenomenon is referred to as “BGA bridging.” The gas pocket may also cause the solder joint to crack and break resulting in an open circuit between the electrical component and the PCB. Additionally, a solder joint with a gas pocket may experience long term reliability issues due to repeated heating and cooling during its operative life.


REFERENCES:
patent: 4764485 (1988-08-01), Loughran et al.
patent: 5477086 (1995-12-01), Rostoker et al.
patent: 5558271 (1996-09-01), Rostoker et al.
patent: 5600180 (1997-02-01), Kusaka et al.
patent: 5742094 (1998-04-01), Ting
patent: 5842275 (1998-12-01), McMillan et al.
patent: 5875102 (1999-02-01), Barrow
patent: 6245594 (2001-06-01), Wu et al.
patent: 6282782 (2001-09-01), Biunno et al.
patent: 6392300 (2002-05-01), Koike
patent: 6395995 (2002-05-01), Joy et al.
patent: 6429389 (2002-08-01), Chung et al.
patent: 6580174 (2003-06-01), McCormick et al.
patent: 6593220 (2003-07-01), Yu et al.
patent: 6631558 (2003-10-01), Burgess
patent: 2002/0084312 (2002-07-01), Shier et al.
patent: 2003/0064546 (2003-04-01), McCormick et al.

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