Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-21
2004-09-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06795959
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to programmable logic devices and, more specifically, to a system and method of determining a time delay of circuitry associated with a field-programmable gate array.
BACKGROUND OF THE INVENTION
Integrated circuits are well known and are extensively used in various present day technological devices and systems, such as sophisticated telecommunications and computer systems. Typically, Application Specific Integrated Circuits (ASICs) provide logic networks for various devices wherein the application has been fully tested. Programmable Logic Devices (PLDs), however, are becoming more widely used, as well.
PLDs are a class of general-purpose chips that can be configured for a wide variety of applications. PLDs include logic devices such as an array of AND gates connected to an array of OR gates. A Field-Programmable Gate Array (FPGA) is a type of PLD that may be advantageously employed to implement tailored logic circuits. In FPGAs, the interconnects between the various elements are designed to be user programmable.
PLDs in general, and FPGAS more specifically, will perform the functions of a custom ASIC but allow more flexibility. In fact, the most significant advantage of using FPGAs is the ability to produce a prototype logic design, and then implement it in silicon, shortly thereafter. An ASIC, however, can take months and many dollars to develop before finally producing a working silicon implementation. Since the introduction of the FPGA in the early 1980s, FPGAs have continued to increase in useable gate count while decreasing in price. Understandably, the decrease in cost along with their design flexibility have made the FPGA a popular choice among engineers and designers.
While considered an advantage, the flexibility of an FPGA can also create a problem when determining the actual delay of a specific circuit implemented within an FPGA. Though determining the delay for an ASIC may also be a concern, the implemented designs have typically undergone extensive testing since they are usually mass produced. This allows the results of one test to be applied to multiple copies of an ASIC. The circuits employed in FPGAs, however, are not mass-produced to the extent of ASICs. Critical circuit portions within an FPGA, therefore, may need to be tested in order to determine actual delays.
While testing can be performed on FPGAs, there are a couple of drawbacks. First, measuring the delay of an FPGA circuit typically requires the use of equipment such as automatic test equipment, vector generators, oscilloscopes, or other complex test equipment. In addition to requiring extensive equipment, determining the delay of a circuit within an FPGA also may require extensive time to set up and dismantle the test equipment.
Second, the needed external test equipment may create delays in addition to the circuit being tested within the FPGA. The intrinsic delays of each piece of equipment along with the effect of their interconnecting leads must be removed from the measured delays to obtain the actual delay of the circuit being tested. These measurements become more problematical when the circuit is tested at higher frequency, since the intrinsic delay may become a larger portion of the delay measurement.
Accordingly, what is needed in the art is a system and method that determines the delay of a circuit within an FPGA without requiring expensive test equipment and creating additional intrinsic delays.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides an integrated delay discriminator for determining a time delay for use with a field-programmable gate array. In one embodiment, the integrated delay discriminator includes a reference path, associated with a first delay of a first portion of the field-programmable gate array and a response path, coupled to the reference path and associated with a second delay of a second portion of the field-programmable gate array. The reference path is configured to provide an event initiation marker for opening a delay measurement window and the response path is configured to provide an event termination marker for closing the delay measurement window thereby allowing a time delay determination measurement between the first portion and the second portion of the field-programmable gate array.
In another aspect, the present invention provides a method of determining a time delay associated with a field-programmable gate array that includes initiating an event initiation marker along a reference path for opening a delay measurement window, receiving an event termination marker along a response path for closing the delay measurement window and providing a time delay determination measurement between the event initiation and the event termination markers.
In another aspect, the present invention provides a field-programmable gate array that includes an integrated delay discriminator and provides a time delay determination measurement between first and second circuits of a field-programmable gate array having first and second time delays, respectively. The integrated delay discriminator includes a reference path and a response path. The reference path, associated with the first circuit, provides an event initiation marker for opening a delay measurement window, and the response path, coupled to the reference path and associated with the second circuit, provides an event termination marker for closing the delay measurement window.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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Dinh Paul
Lattice Semiconductor Corporation
Siek Vuthe
LandOfFree
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