Method for manufacturing a vertical transistor having a storage

Details Method for manufacturing a vertical transistor having a storage Method for manufacturing a vertical transistor having a storage

1996-05-24

1998-01-13

Tsai, Jey

Fishing, trapping, and vermin destroying

437 40GS, 437 40DM, 437 60, 437919, 437 41CS, H01L 218242

Patent

active

057078858

ABSTRACT:
A method for manufacturing a three-dimensionally structured vertical transistor or memory cell including the steps of forming a silicon-on-insulator (SOI) structure on a semiconductor substrate, sequentially depositing a drain region, a channel region and a source region on the SOI substrate structure, a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, to thereby increase the integration of a device. This process and structure avoids the characteristic degradation caused by the leakage current associated with the trench process and structure.

REFERENCES:
patent: 5275960 (1994-01-01), Yamaguchi et al.
patent: 5547903 (1996-08-01), Hsu
patent: 5599724 (1997-02-01), Yoshida

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