Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-18
2004-03-02
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000, C257S401000, C257S510000, C257S512000, C257S513000
Reexamination Certificate
active
06700158
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor technology, and in particular to forming trench DMOS (Double-Diffused Metal Oxide Semiconductor) field effect transistors having enhanced electrical characteristics.
Power field effect transistors (FETs), such as a Metal Oxide Semiconductor FET (or MOSFET), are well known in the semiconductor industry. One type of MOSFET is a double-diffused MOSFET (or DMOS transistor). DMOS transistors typically include: a substrate having a first conductivity type that acts as the drain; an epitaxial layer of the first conductivity type formed over the substrate; a gate electrode formed over the epitaxial layer; source regions of the first conductivity type positioned on opposite sides of the gate electrode; a well having a second conductivity type, which is opposite that of the first conductivity type; and a doped heavy body having the second conductivity type and positioned adjacent each source region on the opposite side of the source region from the gate electrode.
A variation of the DMOS transistor is the “trench” DMOS transistor. The gate of a trench DMOS transistor is defined by one or more trenches that extend vertically downward into an underlying epitaxial layer. Each trench is typically lined with a dielectric material and filled with conductive polysilicon. The source and drain junctions are doped with either n-type or p-type dopants. In either case, the heavy body and well are doped with the oppositely charged dopant type. For example, if the source is n-type, the heavy body and well are doped p-type.
One characteristic of the trench DMOS transistors is the sharp-edged corners that appear at the top and bottom of the trenches following formation of the trenches in both the active cell area and the gate bus area. In operation, high electric fields tend to converge towards these trench corners and, consequently, a lower breakdown voltage of the trench DMOS transistor is observed.
A number of methods have been proposed to round trench corners in order to avoid the low breakdown voltage problem. One method uses a rounding etch followed by a downstream plasma etch. An undesirable side effect of applying the rounding etch, however, is that it causes damages to the sidewalls of the trench and removal of field oxide from the termination structure. This surface damage to the trench sidewalls can contribute to an increase in charge density incorporated in the gate oxide layer formed later on the surface of the trench sidewalls. Removal of field oxide from the termination structure adversely affects device performance. Additionally, the trench rounding process is not totally effective in eliminating the sharp trench corners.
A common technique used to cure trench sidewall surface damage is to grow a sacrificial oxide over the trench sidewalls and then strip the sacrificial oxide. Application of this technique cures the trench sidewall surface damage. However, the sacrificial oxide/strip step increases the trench width, thereby preventing shrinkage of the trench cell.
Finally, in addition to the drawbacks described above, incorporation of the trench rounding and sacrificial oxide/strip step is undesirable since it add more processing steps in the overall trench DMOS transistor fabrication process.
SUMMARY OF THE INVENTION
Generally, the present invention provides a novel method of making a trench MOSFET structure having upper trench corner protection, whereby the need for trench corner rounding or sacrificial oxide/strip steps is obviated. The trench MOSFET structure fabricated according to the method of the present invention exhibits higher oxide breakdown voltage and lower gate-to-source capacitance while reducing the number of processing steps.
In a first aspect of the invention a novel trench MOSFET is disclosed, which provides enhanced upper trench corner protection. The trench MOSFET comprises a substrate over which a masking layer is selectively formed to define a plurality of trench opening accesses. A plurality of trenches are formed through the trench opening accesses and into the substrate. Each trench has a bottom, sidewalls and upper edges extending between end walls of the trench. A dielectric layer lines the bottom and sidewalls of each trench and extends up at least on trench end wall and over a predetermined area of the substrate. A conductive material layer lines the dielectric layer within each trench, the conductive material layer including an extension that extends up in a direction out of the trench and laterally over and above a portion of the predetermined area of the substrate. A portion of the masking layer is formed between the conductive material layer extension and the portion of the dielectric layer overlying the predetermined area of the substrate. Formation of this portion of the masking layer results in increased separation between corners of the trench at the end walls and the conductive material extension, which lies above the predetermined area of the substrate.
In a second aspect of the invention, a novel trench MOSFET is disclosed. The trench MOSFET comprises a substrate into which a trench is formed, the trench having a bottom, sidewalls and upper edges extending between end walls of the trench. A buffer layer lines the bottom and sidewalls of the trench and overlies a portion of the substrate. The buffer layer extends from a predetermined location away from the trench, to an upper edge of the trench end wall, and into the trench. A dielectric layer covers a portion of the buffer layer, including a predetermined portion of the predetermined portion of the buffer layer that extends from the location away from the trench to the upper edge of the trench end wall. Finally, a conductive material layer overlies a predetermined portion of the second dielectric layer and lines the buffer layer.
In a third aspect of the invention, a method of providing a trench MOSFET is disclosed. The first step in the method is to provide a substrate. A masking layer is then formed over the substrate, the masking layer defining a trench opening access. A trench is then formed through the trench opening access and into the substrate, the trench having a bottom, sidewalls and edges extending between end walls of the trench. Next, the bottom and sidewalls of the trench are lined with a dielectric layer. The dielectric layer is also formed to extend up the end wall of the trench and over a predetermined area of the substrate. Then the dielectric layer within the trench is lined with a conductive material layer. The conductive material layer includes an extension that extends up in a direction out of the trench and laterally over and above a portion of the predetermined area of the substrate. Finally, a portion of the masking layer is formed between the conductive material layer extension and the portion of the dielectric layer that overlies the predetermined area of the substrate. It should be emphasized that in this method, the steps are not necessarily listed in sequential order. For example, as described in the detailed specification, the field oxide portion of the dielectric layer is preferably formed first, followed by formation of the masking layer and the gate oxide portion of the dielectric layer.
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patent: 6137152 (2000-10-01), Wu
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patent: 6274905 (2001-08-01), Mo
Cao Densen B.
Probst Dean
Roy Donald J.
Fairchild Semiconductor Corporation
Jackson Jerome
Nguyen Joseph
Townsend and Townsend / and Crew LLP
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