Silicon die with metal feed through structure

Details Silicon die with metal feed through structure Silicon die with metal feed through structure

2001-12-03

2004-01-13

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S459000, C438S613000, C438S620000

Reexamination Certificate

active

06677235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon die and, more particularly, to a silicon die with a metal feed through structure.
2. Description of the Related Art
It is a common practice to permanently connect a silicon die to a semiconductor package. The package often has a multi-layered substrate with internal routing that provides an electrical connection between a number of package bonding pads on the top side of the package, and a number of pins or solder bumps on the bottom side of the package.
Inside the package, very fine bonding wires are used to provide an electrical connection between a number of die bonding pads on the top surface of the die, and the package bonding pads. The die bonding pads, in turn, are electrically connected to a semiconductor integrated circuit.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional ball grid array package
100
. As shown in
FIG. 1
, package
100
includes a substrate
110
that has a top surface
112
and a bottom surface
114
. Substrate
110
also has a number of housing bonding pads
116
that are formed on top surface
112
, and a number of contact pads
120
that are formed on bottom surface
114
. In addition, substrate
110
has a number of solder balls
122
that are attached to contact pads
120
, and internal routing
124
that electrically connects the housing bonding pads
116
to the solder balls
122
via the contact pads
120
. Solder balls
122
, in turn, are shown connected to a printed circuit board
126
As further shown in
FIG. 1
, package
100
also includes a die
130
that is attached to top surface
112
of substrate
110
. Die
130
, in turn, has a number of die bonding pads
132
that are electrically connected to a semiconductor integrated circuit. Package
100
additionally includes a number of very fine bonding wires
134
that connect the housing bonding pads
116
to the die bonding pads
132
, and an encapsulant
136
formed over substrate
110
and die
130
.
One advantage provided by package
100
is that the manufacturing process required to fabricate package
100
is well known and understood. Package
100
, however, suffers from a number of well-known disadvantages. One drawback to housing
100
is that, although the manufacturing process required to fabricate package
100
is well known and understood, package
100
is nonetheless costly to fabricate.
Another drawback to package
100
is that bonding wires
134
have additional inductance which, in turn, decreases the performance of the semiconductor integrated circuit. Thus, there is a need for a method of connecting a die to a semiconductor package that is less expensive than conventional approaches, and eliminates the need for bonding wires.
SUMMARY OF THE INVENTION
The present invention provides a die, and a method of forming the die, that substantially reduce the cost to connect the die to a semiconductor package, and eliminate the need for bonding wires. A semiconductor die formed in accordance with the present invention includes a semiconductor material that has a top surface, a bottom surface, and a doped region that is formed in the top surface of the semiconductor material.
The die also includes a layer of insulation material that is formed on the top surface of the semiconductor material. In addition, the die includes a first conductive contact that is formed through the layer of insulation material to make an electrical connection with the doped region, and a second conductive contact that is formed through the layer of isolation material and the semiconductor material. The second conductive contact extends from the bottom surface of the semiconductor material to the top surface of the layer of isolation material.
In addition, the die includes a first metal-1 trace and a second metal-1 trace. The first metal-1 trace is formed on the layer of insulation material and the first contact to make an electrical connection with the first contact. The second metal-1 trace is formed on the layer of insulation material and the second contact to make an electrical connection with the second contact. The die further includes a layer of isolation material that is formed on the layer of insulation material, the first metal-1 trace, and the second metal-1 trace.
The present invention also includes a method of processing a semiconductor material that has a top surface and a bottom surface. The method includes the steps of forming a doped region in the top surface of the semiconductor material, and forming a trench opening in the semiconductor material. The trench opening has a depth and side walls.
The method also includes the steps of forming a layer of insulation material on the top surface of the semiconductor material, and forming a first opening and a second opening in the layer of insulation material. The first opening exposes the doped region, while the second opening exposes the trench opening.
The method further includes the steps of forming a first contact in the first opening, and a second contact in the second opening and the trench opening. In addition, a layer of metal (metal-1) is formed on the layer of insulation material, the first contact, and the second contact.


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U.S. patent application No. 09/802,148, filed Mar. 8, 2001.

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