Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-11-19
2004-07-20
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000
Reexamination Certificate
active
06765834
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to electronic memory. More particularly, the invention relates to a system and method for sensing memory cells of an array of memory cells.
BACKGROUND OF THE INVENTION
Computing devices require memory. The memory can include read only memory (ROM) or random access memory (RAM). Generally, memory includes memory cells that are arranged in rows and columns. The individual memory cells are accessed through the use of row select lines and column select lines, typically referred to as word lines and bit lines.
FIG. 1
shows an array of random access memory (RAM) cells
110
, a row decoder
120
, a column decoder
130
and associated sense amplifiers
140
. The row decoder
120
selects a row of the array of RAM cells
110
through a word line (WL). The column decoder
130
selects a column of the array of the RAM cell
110
through a bit line (BL). Generally, the sense amplifiers
140
are connectable to the bit lines. The sense amplifiers
140
provide sensing of states of the memory cells.
In a resistive RAM array, the resistance of each memory cell has more than one state. The data in a memory cell can be determined by measuring a resistive state of the cell. The resistive memory cells may include magnetic layers, a fuse or anti-fuse, or any element that stores information affecting a magnitude of a nominal resistance of the memory cell.
Magnetic random access memory (MRAM) is a type of resistive memory. MRAM can include a resistive cross point array of spin dependent tunneling (SDT) junctions. Each SDT junction memory element is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientation, parallel and anti-parallel, represent logic values of “0” and “1.” The magnetization orientation affects the resistance of the SDT junction. The resistance of the SDT junction is a first value if the magnetization orientation is parallel and a second value if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction, and therefore, its logic value may be determined by sensing the resistance of the SDT junction.
Generally, sensing the resistance of an SDT junction requires sensing relatively small signals. The resistance, and therefore, the logical state of an SDT junction can be determined by applying a voltage across the SDT junction and sensing the resultant current, or by applying a current through the SDT junction and sensing the resulting voltage across the SDT junction. SDT junctions include physical characteristics that require sensing either a small amplitude sense current, or a small amplitude sense voltage.
It should be noted that other types of RAM (for example, SRAM and DRAM) do not require the signal noise and interference minimization required by MRAM, because other types of memory generally operate with much larger sense signals.
Prior art MRAM structures generally do not provide efficient use of MRAM sensors. That is, many MRAM sensors of a particular MRAM structure remain unused during an access of information stored within memory cells of the MRAM structure. This limits the capacity to access information within the MRAM structure.
It is desirable to have a system and method for sensing a large number of memory cells of an array of memory cells. It is desirable that sensors used to sense states of the memory cells be efficiently utilized. The system and method should be adaptable for used with arrays of MRAM memory cells.
SUMMARY OF THE INVENTION
The invention includes a system and method for sensing a large number of memory cells of an array of memory cells. The system and method provide for efficient use of sensors that sense the states of the memory cells. The system and method are adaptable for use with MRAM.
An embodiment of the invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit, the array of memory cells including groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers are located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells.
Another embodiment of the invention includes a method of sensing a state of selected memory cells within a memory cell array sensing system. The method includes electrically connecting multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells. Logic states of the multiple memory cells are sensed.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 3643236 (1972-02-01), Kolankowsky et al.
patent: 6188615 (2001-02-01), Perner et al.
Hewlett--Packard Development Company, L.P.
Short Brian R.
Tran M.
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