Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S339000, C257S342000, C257S401000, C257S329000, C257S495000

Reexamination Certificate

active

06674126

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to vertical power semiconductor devices such as MOSFET's (insulated gate field effect transistors), IGBT's (insulated gate bipolar transistors), bipolar transistors and diodes. Specifically, the present invention relates to vertical power semiconductor devices which facilitate realizing a high breakdown voltage and a high current capacity.
BACKGROUND
Semiconductor devices may be classified into lateral devices, which arrange the main electrodes thereof on one major surface and make a drift current flow in parallel to the major surface, and vertical devices, which distribute the main electrodes thereof on two major surfaces facing opposite to each other and makes a drift current flow in perpendicular to the major surfaces. In a vertical semiconductor device, a drift current flows in the thickness direction of the semiconductor chip (vertically) in the ON-state of the semiconductor device and depletion layers expand also in the thickness direction of the semiconductor chip (vertically) in the OFF-state of the semiconductor device.
FIG. 13
, for example, is a cross sectional view of a conventional planar-type n-channel vertical MOSFET.
Referring now to
FIG. 13
, the vertical MOSFET includes a drain electrode
18
on the back surface of a semiconductor chip; an n
+
-type drain layer
11
with low electrical resistance in electrical contact with drain electrode
18
; a very resistive n-type drain drift layer
12
on n
+
-type drain layer
11
; p-type base regions
13
formed, as channel diffusion layers, selectively in the surface portion of n-type drain drift layer
12
; a heavily doped n
+
-type source region
14
formed selectively in the surface portion of p-type base region
13
; a heavily doped p+-type contact region
19
formed selectively in the surface portion of p-type base region
13
for realizing ohmic contact; a polycrystalline silicon gate electrode layer
16
above the extended portion of p-type base region
13
extended between n
+
-type source region
14
and n-type drain drift layer
12
with a gate insulation film
15
interposed therebetween; and a source electrode layer
17
in contact with n+-type source regions
14
and p
+
-type contact regions
19
. Hereinafter, the very resistive drain drift layer will be referred to as an “n-type drift layer” or simply as a “drift layer”.
In the vertical semiconductor device as described above, n-type drift layer
12
works as a layer, through which a drift current flows vertically in the ON state of the MOSFET. In the OFF-state of the MOSFET, n-type drift layer
12
is depleted by the depletion layers expanding in the depth direction thereof (vertically) from the pn-junctions between drift layer
12
and p-type base regions
13
, resulting in a high breakdown voltage.
Thinning very resistive n-type drift layer
12
, that is shortening the drift current path, facilitates substantially reducing the on-resistance (the resistance between the drain and the source), since the drift resistance in the ON-state of the semiconductor device is reduced. However, thinning the very resistive n-type drift layer
12
narrows the width between the drain and the base, for which depletion layers expand from the pn-junctions between drift layer
12
and p-type base regions
13
. Due to the narrow expansion width of the depletion layers, the depletion electric field strength soon reaches the maximum (critical) value for silicon. Therefore, breakdown is caused at a voltage lower than the designed breakdown voltage of the semiconductor device.
A high breakdown voltage is obtained by thickening n-type drift layer
12
. However, a thick n-type drift layer
12
inevitably causes high on-resistance, which further causes on-loss increase. In other words, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage. The tradeoff relation between the on-resistance (current capacity) and the breakdown voltage exists in the other semiconductor devices, which include a drift layer, such as IGBT's, bipolar transistors and diodes.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, Japanese Unexamined Laid Open Patent Application H
09-266311
and Japanese Unexamined Laid Open Patent Application H10-223896 disclose semiconductor devices, which facilitate reducing the tradeoff relation between the on-resistance and the breakdown voltage. The drift layers of the disclosed semiconductor devices are formed of an alternating-conductivity-type drain drift layer including heavily doped n-type regions and heavily doped p-type regions arranged alternately. Hereinafter, the alternating-conductivity-type drain drift layer will be referred to sometimes as the “first alternating conductivity type layer” or simply as the “drain drift region”.
FIG. 14
is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to
FIG. 14
, the drift layer of the vertical MOSFET is not a uniform n-type layer (impurity diffusion layer), but a drain drift region
22
formed of thin n-type drift current path regions
22
a
and thin p-type partition regions
22
b
laminated alternately. Hereinafter, the n-type drift current path regions will be referred to as the “n-type drift regions”. The n-type drift regions
22
a
and p-type partition regions
22
b
are shaped with respective thin layers extending vertically. The bottom of p-type base region
13
is connected with p-type partition region
22
b
. The n-type drift region
22
a
is extended between adjacent p-type base regions
13
and
13
. Although alternating conductivity type layer
22
is heavily doped, a high breakdown voltage is obtained, since alternating conductivity type layer
22
is depleted quickly by the depletion layers expanding laterally in the OFF-state of the MOSFET from the pn-junctions extending vertically across alternating conductivity type layer
22
. Hereinafter, the semiconductor device which includes drain drift region
22
formed of an alternating conductivity type layer will be referred to as the “super-junction semiconductor device”.
In the super-junction semiconductor device as described above, the breakdown voltage is high in the alternating conductivity type layer
22
(drain drift region) below p-type base regions
13
(active region of the semiconductor device) formed in the surface portion of the semiconductor chip. However, the breakdown voltage is low in the breakdown withstanding region around the alternating conductivity type layer
22
(drain drift region), since the depletion layer hardly expands outward from the pn-junction between the outermost p-type base region
13
and n-type drift region
22
a
or to the deep portion of the semiconductor chip, and since the depletion electric field strength soon reaches the critical value for silicon.
To obtain a high breakdown voltage in the breakdown withstanding region outside the outermost p-type base region
13
, a conventional depletion electric field control means such as a guard ring formed on the breakdown withstanding region and a field plate formed on the insulation film may be employed. The breakdown voltage obtained by drain drift region
22
is higher than the breakdown voltage obtained by conventional single-layered drain drift layer
12
. However, the provision of the alternating conductivity type layer makes it more difficult to obtain a higher breakdown voltage in the breakdown withstanding region by adding the conventional depletion electric field control means including the guard ring and the field plate. Therefore, the provision of the alternating conductivity type layer makes it more difficult to optimally design the additional means for correcting the depletion electric field strength in the breakdown withstanding region, and impairs the reliability of the semiconductor device. Thus, it has been impossible to fully realize the functions expectable to the super-junction semiconductor devices.
In power semiconductor devices, p

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