Pre-silicon verification path coverage

Details Pre-silicon verification path coverage Pre-silicon verification path coverage

2002-06-10

2004-05-11

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06735747

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of verifying path coverage in a circuit design generally and, more particularly, to a pre-silicon verification path coverage.
BACKGROUND OF THE INVENTION
Conventional software tools assess path coverage in software when running simulation test benches or doing traces to memory on instrumented code in hardware. Typically, the code is instrumented and the test benches and test cases are developed interactively to achieve the target path coverage level. Flow graphs are provided to reveal what paths have not yet been covered and the resulting information is tied to the code listing. The code commonly runs 4× slower and the tools add 2× to test time. An un-instrumented version of the code is rerun for the regression at full speed to verify no functional differences between the two code sets. In some cases, checking if the path coverage is relevant is also performed. Furthermore, captures of application code running are often performed. However, a lack of verification progress metrics can lead to misuse of available simulation and silicon-based verification resources. In addition, simulation can be thousands to millions of cycles slower and therefore comprehensive simulation is impractical.
SUMMARY OF THE INVENTION
The present invention concerns a method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.
The objects, features and advantages of the present invention include providing a method and architecture that may provide (i) reliable hardware path coverage assessment, (ii) tools that may enable instrumented hardware description language models to have node states save to a trace memory, (iii) a scalable mode capture compression process and/or (iv) tools that may enable hardware trace captures to be presented to simulations tools for path coverage assessment.


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