Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-14
2004-05-11
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S204000, C257S532000
Reexamination Certificate
active
06734487
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to formation of memory integrated circuitry.
BACKGROUND OF THE INVENTION
The reduction in memory cell and other circuit size required for high density dynamic random access memories (DRAMs) and other circuitry is a continuing goal in semiconductor fabrication. Implementing electric circuits involves connecting isolated devices through specific electric paths. When fabricating silicon and other material into integrated circuits, it is necessary to isolate devices built into the substrate from one another. Electrical isolation of devices as circuit density increases is a continuing challenge.
One method of isolating devices involves the formation of a semi-recessed or fully recessed oxide in the non-active (or field) area of the substrate. These regions are typically termed as “field oxide” and are formed by LOCal Oxidation of exposed Silicon, commonly known as LOCOS. One approach in forming such oxide is to cover the active regions with a layer of silicon nitride that prevents oxidation from occurring therebeneath. A thin intervening layer of a sacrificial pad oxide is provided intermediate the silicon substrate and nitride layer to alleviate stress and protect the substrate from damage during subsequent removal of the nitride layer. The unmasked or exposed field regions of the substrate are then subjected to a wet (H
2
O) oxidation, typically at atmospheric pressure and at temperatures of around 1000° C., for two to four hours. This results in field oxide growth where there is no masking nitride.
However at the edges of the nitride, some oxidant also diffuses laterally. This causes the oxide to grow under and lift the nitride edges. Because the shape of the oxide at the nitride edges is that of a slowly tapering oxide wedge that merges into another previously formed layer of oxide, it has commonly been referred to as a “bird's beak”. The bird's beak is a lateral extension or encroachment of the field oxide into the active areas where the devices are formed. Although the length of the bird's beak depends upon a number of parameters, the length is typically from 0.05 micron-0.15 micron per side.
This thinner area of oxide resulting from the bird's beak provides the disadvantage of not providing effective isolation in these regions, and as well unnecessarily consumes precious real estate on the semiconductor wafer. Further, as circuit density commonly referred to as device pitch falls below 1.0 micron, conventional LOCOS techniques begin to fail due to excessive encroachment of the oxide beneath the masking stack. The closeness of the masking block stacks in such instances can result in effective joining of adjacent bird's beaks, thus effectively lifting the masking stacks and resulting in no masking effect to the oxidation. To prevent this, LOCOS active area masks typically need to be spaced further apart than the minimum capable photolithographic feature dimension where such falls below 0.3 micron, especially where 2-dimensional encroachment occurs.
The problem is exemplified in FIG.
1
. There illustrated is an array
10
of staggered active area regions or islands
11
,
12
,
13
and
14
of a dynamic random access memory array. The areas surrounding each of the subject islands would constitute LOCOS field oxide. Active area islands
11
and
13
are formed along a line
15
along which a plurality of DRAM cells are ultimately formed. Islands
12
and
14
form a part of another line along which DRAM cells of the array are formed. Dimension
16
constitutes a separation distance between adjacent lines of active area, whereas dimension
18
constitutes the separation distance between adjacent active areas in the same line.
Unfortunately, dimension
18
typically ends up being at least 1.5 times as great as dimension
16
because of the bird's beak encroachment in two directions. Specifically, the ends of the desired active areas are subjected to bird's beak oxide encroachment both from the ends of the desired active area regions as well as laterally from the sides of such regions. However at the lateral edges of the particular active area mask not at an end, such as where the arrowhead of dimension
16
in region
11
is shown contacting the active area edge, the field oxide mask is only exposed to one dimensional oxide encroachment, that being only from laterally outside. Accordingly, the degree of encroachment is not as great along the edges as at the ends of the active area masks.
The
FIG. 1
illustrated layout is typically utilized to result in individual memory cells throughout the array occupying area equal to 8F
2
. A folded bit line array architecture is also utilized to provide acceptable and superior signal-to-noise performance in conjunction with the 8F
2
cell array.
LOCOS field oxide isolation is generally accepted within the industry to fail when the minimum photolithographic feature dimension falls below 0.3 micron due to the above end-to-end encroachment. The typical alternate isolation technique in such instances is trench isolation. For example, an article by Chatterjee et al. from the 1996 Symposium On VLSI Technology Digest Of Technical Papers, at page 156, entitled, “A Shallow Trench Isolation Study For 0.25/0.18 Micron CMOS Technologies and Beyond”, provides that “As high performance CMOS technology is scaled down to the current 0.35-0.25 micron generation, shallow trench isolation (STI) becomes indispensable due to its advantages compared to the conventional LOCOS-type isolation, viz. smaller channel-width encroachment, better isolation/latch-up characteristics, planar topography, and smaller junction edge capacitance.” [emphasis added] In STI, trenches are formed in the semiconductive substrate and filled with oxide such that the LOCOS bird's beak is eliminated. Trench isolation does, however, have its own other processing drawbacks.
SUMMARY
In one aspect, the invention provides memory integrated circuitry having at least some individual memory cell size of less than 8F
2
, where “F” is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array. In one preferred implementation, adjacent memory cells are isolated from one another by field oxide where “F” is no greater than 0.25 micron. In another aspect, at least some of those memory cells of the array are formed in lines of active area which are continuous between adjacent memory cells in the line, with said adjacent memory cells being isolated from one another by a conductive line over said continuous active area between said adjacent memory cells. In yet another aspect, the invention provides the memory circuitry in the form of DRAM having word lines and bit lines, with the bit lines preferably comprising D and D* lines formed in a folded bit line architecture within the array.
REFERENCES:
patent: 5045899 (1991-09-01), Arimoto
patent: 5107459 (1992-04-01), Chu et al.
patent: 5350706 (1994-09-01), McElroy et al.
patent: 5383151 (1995-01-01), Onishi et al.
patent: 5469383 (1995-11-01), McElroy et al.
patent: 5508541 (1996-04-01), Hieda et al.
patent: 5537347 (1996-07-01), Shiratake et al.
patent: 5595928 (1997-01-01), Lu et al.
patent: 5637528 (1997-06-01), Higashitani et al.
patent: 5665623 (1997-09-01), Liang et al.
patent: 5726092 (1998-03-01), Mathews et al.
patent: 5736670 (1998-04-01), Carbonell et al.
patent: 5747844 (1998-05-01), Aoki et al.
patent: 5756390 (1998-05-01), Juengling et al.
patent: 6297129 (2001-10-01), Tran et al.
patent: 03205868 (1991-09-01), None
Fazan, P.C., et al., “A High-C Capacitor (20.4.fF/um sq) with Ultrathin CVD-Ta2O5 Films Deposited on Rugged Poly-Si for High Density DRAMs”, 1992, IEDM 92, pp. 263-266.*
Fazan et al., “A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs,” ©1993 IEEE, 4 pages.
A. Chatterjee et al., “A S
Reinberg Alan R.
Tran Luan
Fahmy Wael
Micro)n Technology, Inc.
Weiss Howard
Wells St. John P.S.
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