Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-17
2004-07-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S239000, C257S261000, C257S316000, C257S298000, C438S201000, C438S211000, C438S216000, C438S257000, C438S593000
Reexamination Certificate
active
06759709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device.
2. Description of the Background Art
In a nonvolatile semiconductor memory device having a two-layer-gate structure, a source line is frequently formed in a self-alignment manner (SAS: Self Aligned Source) to reduce a pattern size of elements (for example, Japanese Laid-open Patent No. HB-102531) In such a nonvolatile semiconductor memory device, an element isolation insulating film is formed on a semiconductor substrate in a certain direction in the shape of a stripe, and a control gate electrode is formed in the shape of a stripe in a direction perpendicular to the element isolation insulating film. After the element isolation insulating film is removed by etching, a source line is formed in a self-alignment manner, i.e. by injecting an impurity ion using the control gate electrode as a mask. When the source line is formed by such a method, a memory cell can reduce its pattern size without an alignment error between the source line and the control gate electrode.
SUMMARY OF THE INVENTION
In the conventional nonvolatile semiconductor memory device, an impurity is diffused to a silicon substrate to form a source line after an element isolator film is removed. Since recesses are formed on the surface of the silicon substrate by removing the element isolation insulating film, a source line resistance is increased for the following reasons: A current in the source line started from the source region flows toward the source region of adjacent cells through the side surface, the bottom surface, and the side surface of the recessed portion. Therefore an effective source line length is larger than an apparent source line length by the length of the side surface of the recessed portion. In addition, since an impurity injection in the side surface of the recessed portion is more difficult than the bottom surface of the recessed portion, the side surface of the recession tends to have a high resistance. Thus, the resistance of the source line is increased.
This problem becomes serious when a memory cell is reduced in size for a high degree of integration. In particular, when trench element isolation is performed, in which an element isolation film is buried in a trench (=groove) formed in a semiconductor substrate, the problem becomes more serious. In the trench element isolation, a recessed portion is formed in the surface of the silicon substrate corresponding to the depth of the trench. The depth of the trench hardly changes, even when a gate width (W) of the memory cell is reduced. For this reason, as the memory cell reduces in size, a ratio of the source line length between adjacent memory cells to the size of the memory cell in the direction of the gate width (W) increases. This increases a source line resistance per unit bit.
Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device that has a low source line resistance and good scalability.
According to the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a semiconductor substrate,
a plurality of memory cells arranged in the form of a matrix on said semiconductor substrate, each of said memory cells including transistors having floating gate electrodes and control gate electrodes;
element isolation insulating films for isolating said memory cells; and
source lines formed in a self-alignment manner with respect to said control gate electrodes;
wherein the surface of said semiconductor substrate has such a periodical unevenness along said source lines that the portions of said memory cells form projection portions and the portions where said element isolation insulating films have removed form recess portions;
each of said source lines has a diffusion layer that an impurity is distributed along the surface of said semiconductor substrate and a buried diffusion layer that an impurity is distributed at a position deeper than said diffusion layer;
and said buried diffusion layer connects a plurality of portions of said diffusion layers under the bottom surface of said recess portion to each other.
REFERENCES:
patent: 5817556 (1998-10-01), Sasaki
patent: 6306737 (2001-10-01), Mehrad et al.
patent: 6337244 (2002-01-01), Prall et al.
patent: 8-102531 (1996-04-01), None
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