Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-18
2004-09-21
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06795957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to computer-aided design (CAD) tools for generating integrated circuit (IC) layouts, and particular to a method such a CAD tool can employ to design vias for interconnecting overlapping power wires in an IC layout.
2. Description of Related Art
A power wire is a conductor formed within an IC for conveying a power or ground signal, and power wires formed on more than one layout of an IC may convey the same power or ground signal. To make an IC's power distribution network robust, a CAD tool generating an IC layout should provide conductive vias extending vertically between overlapping power wires carrying the same power or ground signal. Ideally the layout tool should size and position the vias within the planar area of power wire overlap to provide maximum current carrying capacity between the two power wires.
Accordingly, as illustrated in
FIG. 27
, when a layout tool adds a power wire
120
to a layout that overlaps an existing power wire
122
residing on another layer of the layout, the layout tool forms vias in the rectangular area
124
of vertical overlap. Since vias are typically provided only in a limited range of dimensions, the layout tool sizes and arranges the vias to be formed in area
124
in a way that maximizes the amount of area
124
occupied by vias.
As illustrated in
FIG. 28
, when the layout tool adds another power wire
126
to the layout adjacent to wire
120
, the layout tool finds an area
128
of overlap between new wire
126
and existing wire
122
and therefore designs a via layout in area
128
to link power wires
122
and
126
. This progressive, wire-by-wire method of determining where to form vias does not always make the most efficient use of the available space in which to places vias. For example the layout tool would likely be able to make more efficient use of the space occupied by areas
124
and
128
with respect to the current carrying capacity of vias formed in those areas, if it were to treat the two via areas
124
and
128
as a single larger area, and generate the via layout for that larger area as a unified design rather than to design separate via layouts for the two areas
124
and
128
.
Therefore what is needed is a computationally efficient method that can be employed by an IC layout tool to group areas of power wire overlap to be filled with vias in a way that enables the layout tool to design via layouts providing maximal current carrying capacity between overlapping power wires.
BRIEF SUMMARY OF THE INVENTION
An IC layout tool employing a method in accordance with the invention determines areas of an IC layout in which to provide power wire interconnection vias by first querying a “world” HV tree that keeps track of positions of power wires and other objects within the IC layout to determine overlapping areas of power wires residing on differing layers of the layout.
The layout tool then creates a separate “via” HV tree identifying positions of a separate set of one or more “via boxes” for each identified area of power wire overlap, wherein each via box of the set spans an area of a separate one of the IC layers residing between the overlapping power wires. The layout tool then modifies the via HV tree to partition each via box spanning an object acting as a via obstruction into a set of smaller via boxes occupying all unobstructed areas of the partitioned via box. The layout tool also merges adjacent via boxes residing on the same IC layers to create larger via boxes. The tool then modifies the IC layout to provide vias in the areas of each layer identified by the via HV tree as being occupied by a via box.
A layout tool can usually design a large via structure (filling a large area) that is capable of handling more current than several smaller via structures it might design to fill several small adjacent areas spanning the same total area as the larger via. Therefore by merging small overlapping or abutting via boxes residing on the same layer into larger via boxes, the method helps to maximize the current carrying capacity of vias the layout tool designs for interconnecting power wires. Using a via HV tree to keep track of spaces in which the layout tool may provide power vias increases the speed of the method because an HV tree can quickly locate areas of objects residing on the same or differing layers overlap or abut one another.
The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant(s) consider to be the best mode(s) of practicing the invention, together with further advantages and objects of the invention, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.
REFERENCES:
Enbody, R.J., et al., “Near-optimal n-layer channel routing”, IEEE, 1986, pp. 708-714*
Xiang, Hua et al., “ECO algorithms for removing overlaps between power rails and signal wires”, IEEE, 2002, pp. 67-74.*
Dupenlaup, Guy, “A wire routing scheme for double-layer cell arrays”, IEEE, 1984, pp. 32-37.*
Bentley, Jon Louis, “Multidimensional binary search trees used for associative searching”, IEEE, 1975, pp. 509-517.*
Shenoy, N.V., et al., “An efficient routing database”, IEEE, 2002, pp. 590-595.*
Lai, Glenn G., et al., “HV/VH trees: a new spatial data stucture for fast region queries”, IEEE, 1993, pp. 43-47.
Lai Glenn
Lee Jong Chang
Bedell Daniel J.
Cadence Design Systems Inc.
Smith-Hill and Bedell
Whitmore Stacy A.
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