Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-12
2004-05-18
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S333000, C257S339000, C257S476000
Reexamination Certificate
active
06737704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to transistors and, more particularly, to power MOSFETs which are used in most power supply circuits and the like.
2. Description of the Related Art
Reference number
101
in
FIGS. 43 and 44
represents a trench type power MOSFET according to the related art.
FIG. 44
is a sectional view taken along the line C—C in FIG.
43
.
As shown in
FIG. 44
, the power MOSFET
101
has a semiconductor substrate
105
provided by forming a drain layer
112
constituted by an n
−
-type epitaxial layer and p-type body regions
115
on an n
+
-type silicon substrate
111
sequentially. The power MOSFET
101
also has a plurality of cells
103
as shown in FIG.
43
. The plurality of rectangular cells
103
is formed in a staggered configuration on a top surface of the semiconductor substrate
105
.
FIG. 43
shows six cells
103
1
through
103
6
and omits a source electrode film which will be described later.
As shown in
FIG. 44
, a trench
118
having a rectangular section whose bottom extends into the drain layer
112
is formed in the p-type body region
115
of each cell
103
, and a p
+
-type diffusion region
124
extending to a predetermined depth from the top surface of the p-type body region
115
is formed in a position between adjacent trenches
118
. An n
+
-type source region
127
extending to a depth short of the drain layer
112
from the surface of the p-type body region
115
is formed around the p
+
-type diffusion region
124
and around the opening of the trench.
A gate insulating film
119
is formed on the inner circumferential surface and the bottom surface of the trench
118
, and a polysilicon gate
130
is formed on the surface of the gate insulating film
119
such that it fills the interior of the trench
118
and such that the upper end thereof is located higher than the lower end of the source region
127
.
A PSG (phosphosilicate glass) film
128
is formed on top of the polysilicon gate
130
, and a source electrode film
129
made of Al is formed to coat the top surfaces of the PSG film
128
and the semiconductor substrate
105
. The polysilicon gate
130
and source electrode film
129
are electrically insulated by the PSG film
128
.
In a power MOSFET
101
having such a structure, when a voltage equal to or higher than a threshold voltage is applied across the polysilicon gates
130
and the source electrode film
129
with a high voltage applied across the source electrode film
129
and drain layer
112
, inversion layers are formed at interfaces between the gate oxide films
119
and p-type body regions, and a current flows from the drain to the source through the inversion layers.
In a power MOSFET
101
having the above-described structure, the PSG films
128
must be patterned using photolithography to provide direct contact between the source electrode film
129
and each of the source regions
127
on the top surfaces of the source regions
127
. Since misalignment of the PSG films
128
can occur when they are formed using such a method, the area occupied by the PSG films
128
on the top surface of the semiconductor substrate
105
includes some margin to ensure insulation between the source electrode film
129
and polysilicon gates
130
even if there is some misalignment.
Consequently, the PSG films
128
are formed not only above the trench
118
but also around the openings of the trench.
The parts of the source regions
127
formed around the openings of the trench
118
are therefore located under the PSG films
128
and, in order to provide contact between the source electrode film
129
and the source regions
127
with a sufficiently low resistance, a large area of the source regions
127
must be exposed in advance on the top surface of the semiconductor substrate. As a result, the area occupied by the source regions
127
on the top surface of the semiconductor substrate
105
can not be reduced beyond a certain limit, and this has hindered efforts toward finer devices.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the above-described problems with the related art, and it is an object of the invention to provide a technique which makes it possible to reduce the area occupied by cells to be formed on a substrate, thereby allowing a reduction of the size of devices.
In order to solve the above-described problems, according to a first aspect of the invention, there is provided a transistor having:
a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type provided on the semiconductor layer and an oppositely conductive region of a second conductivity type provided on the drain layer;
a trench provided such that it extends from a top surface of the oppositely conductive region to the drain layer;
a source region of the first conductivity type provided in the oppositely conductive region and exposed on an inner circumferential surface of the trench;
a gate insulating film provided on the inner circumferential surface and inner bottom surface of the trench such that it reaches to the drain layer, the oppositely conductive region and the source region;
a gate electrode material provided in tight contact with the gate insulating film;
a source electrode film provided in contact with at least the source region exposed on the inner circumferential surface of the trench and electrically insulated from the gate electrode material.
According to a second aspect of the invention, there is provided a transistor having a drain electrode film formed on a surface of the semiconductor layer opposite to the drain layer.
According to a third aspect of the invention, there is provided a transistor in which the impurity concentration of the semiconductor layer is higher than the impurity concentration of the drain layer.
According to a fourth aspect of the invention, there is provided a transistor having an insulating material thicker than the gate insulating film provided between the gate electrode material in the trench and the source electrode film.
According to a fifth aspect of the invention, there is provided a transistor in which the insulating material is any one of a silicon oxide film, a combination of a silicon oxide film and PSG film, a combination of silicon oxide film and a BPSG film, and a combination of a silicon oxide film and a silicon nitride film.
According to a sixth aspect of the invention, there is provided a transistor in which the insulating material has a thickness between 0.01 &mgr;m and 1.0 &mgr;m inclusive.
According to a seventh aspect of the invention, there is provided a transistor in which the trench is provided in the form of a mesh on a top surface of the semiconductor substrate and in which the source region is provided in contact with the trench.
According to an eighth aspect of the invention, there is provided a transistor in which the semiconductor layer is of the first conductivity type.
According to a ninth aspect of the invention, there is provided a transistor in which the semiconductor layer is of the second conductivity type as opposed to the drain layer.
According to a tenth aspect of the invention, there is provided a transistor having:
a semiconductor substrate having a drain layer of a first conductivity type and an oppositely conductive region of a second conductivity type provided on said drain layer;
a trench provided such that it extends from a surface of said oppositely conductive region to said drain layer;
a source region of the first conductivity type provided in said oppositely conductive region and exposed on an inner circumferential surface of said trench;
a gate insulating film provided on the inner circumferential surface and inner bottom surface of said trench such that it reaches to said drain layer, said oppositely conductive region and said source region;
a gate electrode material provided in tight contact with said gate insulating film;
a source electrode film provided in contact with at least said source reg
Takemori Toshiyuki
Watanabe Yuji
Armstrong, Kratz, Quintos Hanson & Brooks, LLP.
Pham Long
Rao Shrinivas H.
Shindengen Electric Manufacturing Co. Ltd.
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